The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이전 연구에서 우리는 ATM 스위치 내에서 최악의 셀 지연을 도출했으며 따라서 일련의 실시간 연결에 대한 최악의 종단 간 지연을 찾을 수 있습니다. 우리는 이러한 지연이 연결의 우선순위 할당에 민감하다는 것을 관찰했습니다. 스위치 내에서 더 나은 우선순위 할당 방식을 사용하면 최악의 경우 지연을 줄이고 더 나은 네트워크 성능을 제공할 수 있습니다. 우리는 폐쇄형 분석에 대한 이전 작업을 확장하여 다양한 우선순위 할당과 시스템 매개변수가 성능에 어떤 영향을 미칠 수 있는지에 대한 더 많은 실험적 연구를 수행했습니다. 또한 규제된 ATM 스위치에 대한 최악의 지연 분석을 통해 각 연결에 대한 출력 컨트롤러의 누출 버킷으로 네트워크 트래픽을 원활하게 할 수 있습니다. Leaky Bucket 매개변수를 적절하게 설정하면 스위치 지연을 늘리지 않고도 네트워크 트래픽의 버스트를 줄일 수 있습니다. 따라서 스위치 내 각 활성 연결에 필요한 버퍼 수가 더 적습니다. 본 논문의 실험 결과는 각 연결에 대해 버퍼 요구 사항을 최대 5.75%까지 줄일 수 있다는 것을 보여 주었습니다. 이는 규제된 ATM 네트워크 내에서 수백 개의 연결이 스위치를 통과할 때 상당한 의미가 있을 수 있습니다.
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부
Joseph NG, "On Traffic Burstiness and Priority Assignment for the Real-Time Connections in a Regulated ATM Network" in IEICE TRANSACTIONS on Communications,
vol. E82-B, no. 6, pp. 841-850, June 1999, doi: .
Abstract: From our previous studies, we derived the worst case cell delay within an ATM switch and thus can find the worst case end-to-end delay for a set of real-time connections. We observed that these delays are sensitive to the priority assignment of the connections. With a better priority assignment scheme within the switch, the worst case delay can be reduced and provide a better network performance. We extend our previous work on the closed form analysis to conduct more experimental study of how different priority assignments and system parameters may affect the performance. Furthermore, from our worst case delay analysis on a regulated ATM switch, network traffic can be smoothed by a leaky bucket at the output controller for each connection. With the appropriate setting on the leaky bucket parameter, the burstiness of the network traffic can be reduced without increasing the delay in the switch. Therefore, fewer buffers will be required for each active connection within the switch. In this paper, our experimental results have shown that the buffer requirement can be reduced up to 5.75% for each connection, which could be significant, when hundreds of connections are passing through the switches within a regulated ATM network.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e82-b_6_841/_p
부
@ARTICLE{e82-b_6_841,
author={Joseph NG, },
journal={IEICE TRANSACTIONS on Communications},
title={On Traffic Burstiness and Priority Assignment for the Real-Time Connections in a Regulated ATM Network},
year={1999},
volume={E82-B},
number={6},
pages={841-850},
abstract={From our previous studies, we derived the worst case cell delay within an ATM switch and thus can find the worst case end-to-end delay for a set of real-time connections. We observed that these delays are sensitive to the priority assignment of the connections. With a better priority assignment scheme within the switch, the worst case delay can be reduced and provide a better network performance. We extend our previous work on the closed form analysis to conduct more experimental study of how different priority assignments and system parameters may affect the performance. Furthermore, from our worst case delay analysis on a regulated ATM switch, network traffic can be smoothed by a leaky bucket at the output controller for each connection. With the appropriate setting on the leaky bucket parameter, the burstiness of the network traffic can be reduced without increasing the delay in the switch. Therefore, fewer buffers will be required for each active connection within the switch. In this paper, our experimental results have shown that the buffer requirement can be reduced up to 5.75% for each connection, which could be significant, when hundreds of connections are passing through the switches within a regulated ATM network.},
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - On Traffic Burstiness and Priority Assignment for the Real-Time Connections in a Regulated ATM Network
T2 - IEICE TRANSACTIONS on Communications
SP - 841
EP - 850
AU - Joseph NG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E82-B
IS - 6
JA - IEICE TRANSACTIONS on Communications
Y1 - June 1999
AB - From our previous studies, we derived the worst case cell delay within an ATM switch and thus can find the worst case end-to-end delay for a set of real-time connections. We observed that these delays are sensitive to the priority assignment of the connections. With a better priority assignment scheme within the switch, the worst case delay can be reduced and provide a better network performance. We extend our previous work on the closed form analysis to conduct more experimental study of how different priority assignments and system parameters may affect the performance. Furthermore, from our worst case delay analysis on a regulated ATM switch, network traffic can be smoothed by a leaky bucket at the output controller for each connection. With the appropriate setting on the leaky bucket parameter, the burstiness of the network traffic can be reduced without increasing the delay in the switch. Therefore, fewer buffers will be required for each active connection within the switch. In this paper, our experimental results have shown that the buffer requirement can be reduced up to 5.75% for each connection, which could be significant, when hundreds of connections are passing through the switches within a regulated ATM network.
ER -