The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
우리는 높은 비트율 무선 시스템에서 심볼율 근처에서 작동할 수 있는 PSBTR(교란 샘플링 BTR)이라는 새로운 BTR(비트 타이밍 복구) 방식을 제안합니다. PSBTR 방식에서는 듀티 팩터가 50%가 아닌 독특한 샘플 클럭이 사용됩니다. 우리는 이러한 유형의 시계를 교란된 샘플 시계라고 부르며 이를 시계 복구에 사용합니다. PSBTR에서는 샘플 클럭의 사이클 슬립이 없으며 PSBTR 회로는 대부분 디지털입니다. 우리는 컴퓨터 시뮬레이션과 실험을 통해 AWGN(Additive White Gaussian Noise) 하에서 PSBTR 방식의 성능을 조사하고, 이러한 결과로부터 PSBTR 회로의 성능과 회로 매개변수 간의 관계를 명확히 합니다. 전반적인 결과는 PSBTR 방식이 잘 수행되고 높은 비트율 무선 시스템을 위한 BTR 방식으로 사용될 수 있음을 나타냅니다.
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부
Toshiaki TAKAO, Yoshifumi SUZUKI, Tadashi SHIRATO, "A New Digitized Bit Timing Recovery Scheme Using a Perturbed Sample Timing Technique for High-Bit-Rate Wireless Systems" in IEICE TRANSACTIONS on Communications,
vol. E82-B, no. 8, pp. 1326-1333, August 1999, doi: .
Abstract: We propose a new bit timing recovery (BTR) scheme, called perturbed sampling BTR (PSBTR), that can operate near the symbol rate in high-bit-rate wireless systems. A peculiar sample clock, the duty factor of which is not 50%, is used in the PSBTR scheme. We call this type of clock a perturbed sample clock and use it for clock recovery. In PSBTR, there is no cycle slip of the sample clock, and the PSBTR circuit is mostly digital. We examine the performance of the PSBTR scheme under additive white Gaussian noise (AWGN) by computer simulation and experiment, and from these results, clarify the relationship between the performance and circuit parameters of the PSBTR circuit. The overall results indicate that the PSBTR scheme performs well and can be employed as a BTR scheme for high-bit-rate wireless systems.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e82-b_8_1326/_p
부
@ARTICLE{e82-b_8_1326,
author={Toshiaki TAKAO, Yoshifumi SUZUKI, Tadashi SHIRATO, },
journal={IEICE TRANSACTIONS on Communications},
title={A New Digitized Bit Timing Recovery Scheme Using a Perturbed Sample Timing Technique for High-Bit-Rate Wireless Systems},
year={1999},
volume={E82-B},
number={8},
pages={1326-1333},
abstract={We propose a new bit timing recovery (BTR) scheme, called perturbed sampling BTR (PSBTR), that can operate near the symbol rate in high-bit-rate wireless systems. A peculiar sample clock, the duty factor of which is not 50%, is used in the PSBTR scheme. We call this type of clock a perturbed sample clock and use it for clock recovery. In PSBTR, there is no cycle slip of the sample clock, and the PSBTR circuit is mostly digital. We examine the performance of the PSBTR scheme under additive white Gaussian noise (AWGN) by computer simulation and experiment, and from these results, clarify the relationship between the performance and circuit parameters of the PSBTR circuit. The overall results indicate that the PSBTR scheme performs well and can be employed as a BTR scheme for high-bit-rate wireless systems.},
keywords={},
doi={},
ISSN={},
month={August},}
부
TY - JOUR
TI - A New Digitized Bit Timing Recovery Scheme Using a Perturbed Sample Timing Technique for High-Bit-Rate Wireless Systems
T2 - IEICE TRANSACTIONS on Communications
SP - 1326
EP - 1333
AU - Toshiaki TAKAO
AU - Yoshifumi SUZUKI
AU - Tadashi SHIRATO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E82-B
IS - 8
JA - IEICE TRANSACTIONS on Communications
Y1 - August 1999
AB - We propose a new bit timing recovery (BTR) scheme, called perturbed sampling BTR (PSBTR), that can operate near the symbol rate in high-bit-rate wireless systems. A peculiar sample clock, the duty factor of which is not 50%, is used in the PSBTR scheme. We call this type of clock a perturbed sample clock and use it for clock recovery. In PSBTR, there is no cycle slip of the sample clock, and the PSBTR circuit is mostly digital. We examine the performance of the PSBTR scheme under additive white Gaussian noise (AWGN) by computer simulation and experiment, and from these results, clarify the relationship between the performance and circuit parameters of the PSBTR circuit. The overall results indicate that the PSBTR scheme performs well and can be employed as a BTR scheme for high-bit-rate wireless systems.
ER -