The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
다중 QoS MSDA(Scalable-Distributed-Arbitration) ATM 스위치는 HOL 우선순위 규정에 따라 높은 우선순위 및 낮은 우선순위 트래픽을 모두 지원합니다. 이는 각각 높은 우선순위 및 낮은 우선순위 버퍼로 구성된 교차점 및 전송 버퍼를 사용합니다. 버퍼는 전송할 셀의 선택을 분산 방식으로 조정합니다. MSDA 스위치는 이전에 설명한 단일 QoS SSDA(확장 가능 분산 중재) 스위치의 확장성을 제공하면서 여러 QoS 클래스를 지원합니다. SSDA 스위치에서 사용되는 지연 시간 기반 셀 선택 메커니즘을 우선 순위가 낮은 트래픽에 적용하면 처리량 측면에서 공정성을 달성할 수 없다는 문제가 발생합니다. 이 문제는 우선순위가 낮은 트래픽에 대해 각 교차점에 분산형 링 중재자 기반 셀 선택 메커니즘을 도입함으로써 극복됩니다. 각 교차점의 우선순위가 낮은 전송 버퍼에는 각 상위 입력 포트마다 하나씩 가상 대기열이 있습니다. 낮은 우선순위 트래픽을 위한 셀은 낮은 우선순위 교차점 버퍼와 이러한 가상 대기열 간의 분산 링 중재에 의해 선택됩니다. 우선순위가 높은 트래픽의 경우 SSDA 스위치와 동일한 지연 시간 기반 셀 선택 메커니즘이 사용됩니다. 시뮬레이션 결과, MSDA 스위치는 우선 순위가 높은 트래픽에 대해서는 지연 시간의 공정성을 보장하고 우선 순위가 낮은 트래픽에 대해서는 처리량 측면에서 공정성을 보장하는 것으로 나타났습니다.
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Eiji OKI, Naoaki YAMANAKA, Masayoshi NABESHIMA, "Performance of Scalable-Distributed-Arbitration ATM Switch Supporting Multiple QoS Classes" in IEICE TRANSACTIONS on Communications,
vol. E83-B, no. 2, pp. 204-213, February 2000, doi: .
Abstract: A multi-QoS scalable-distributed-arbitration (MSDA) ATM switch is described that supports both high- and low-priority traffic under the head-of-line-priority discipline. It uses crosspoint and transit buffers, each consisting of a high- and low-priority buffer. The buffers arbitrate in a distributed manner the selection of which cellsto transmit. The MSDA switch supports multiple QoS classes while still providing the scalability of a previously described single-QoS scalable-distributed-arbitration (SSDA) switch. A problem occurs when the delay-time-based cell-selection mechanism used in the SSDA switch is applied to the low-priority traffic: it cannot achieve fairness in terms of throughput. This problem is overcome by introducing a distributed-ring-arbiter-based cell-selection mechanism at each crosspoint for the low-priority traffic. The low-priority transit buffer at each crosspoint has virtual queues, one for each upper input port. Cells for the low-priority traffic are selected by distributed-ring arbitration among the low-priority crosspoint buffer and these virtual queues. For the high-priority traffic, the same delay-time-based cell-selection mechanism is used as in the SSDA switch. Simulations show that the MSDA switch ensures fairness interms of delay time for the high-priority traffic and ensures fairness in terms of throughput for the low-priority traffic.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e83-b_2_204/_p
부
@ARTICLE{e83-b_2_204,
author={Eiji OKI, Naoaki YAMANAKA, Masayoshi NABESHIMA, },
journal={IEICE TRANSACTIONS on Communications},
title={Performance of Scalable-Distributed-Arbitration ATM Switch Supporting Multiple QoS Classes},
year={2000},
volume={E83-B},
number={2},
pages={204-213},
abstract={A multi-QoS scalable-distributed-arbitration (MSDA) ATM switch is described that supports both high- and low-priority traffic under the head-of-line-priority discipline. It uses crosspoint and transit buffers, each consisting of a high- and low-priority buffer. The buffers arbitrate in a distributed manner the selection of which cellsto transmit. The MSDA switch supports multiple QoS classes while still providing the scalability of a previously described single-QoS scalable-distributed-arbitration (SSDA) switch. A problem occurs when the delay-time-based cell-selection mechanism used in the SSDA switch is applied to the low-priority traffic: it cannot achieve fairness in terms of throughput. This problem is overcome by introducing a distributed-ring-arbiter-based cell-selection mechanism at each crosspoint for the low-priority traffic. The low-priority transit buffer at each crosspoint has virtual queues, one for each upper input port. Cells for the low-priority traffic are selected by distributed-ring arbitration among the low-priority crosspoint buffer and these virtual queues. For the high-priority traffic, the same delay-time-based cell-selection mechanism is used as in the SSDA switch. Simulations show that the MSDA switch ensures fairness interms of delay time for the high-priority traffic and ensures fairness in terms of throughput for the low-priority traffic.},
keywords={},
doi={},
ISSN={},
month={February},}
부
TY - JOUR
TI - Performance of Scalable-Distributed-Arbitration ATM Switch Supporting Multiple QoS Classes
T2 - IEICE TRANSACTIONS on Communications
SP - 204
EP - 213
AU - Eiji OKI
AU - Naoaki YAMANAKA
AU - Masayoshi NABESHIMA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E83-B
IS - 2
JA - IEICE TRANSACTIONS on Communications
Y1 - February 2000
AB - A multi-QoS scalable-distributed-arbitration (MSDA) ATM switch is described that supports both high- and low-priority traffic under the head-of-line-priority discipline. It uses crosspoint and transit buffers, each consisting of a high- and low-priority buffer. The buffers arbitrate in a distributed manner the selection of which cellsto transmit. The MSDA switch supports multiple QoS classes while still providing the scalability of a previously described single-QoS scalable-distributed-arbitration (SSDA) switch. A problem occurs when the delay-time-based cell-selection mechanism used in the SSDA switch is applied to the low-priority traffic: it cannot achieve fairness in terms of throughput. This problem is overcome by introducing a distributed-ring-arbiter-based cell-selection mechanism at each crosspoint for the low-priority traffic. The low-priority transit buffer at each crosspoint has virtual queues, one for each upper input port. Cells for the low-priority traffic are selected by distributed-ring arbitration among the low-priority crosspoint buffer and these virtual queues. For the high-priority traffic, the same delay-time-based cell-selection mechanism is used as in the SSDA switch. Simulations show that the MSDA switch ensures fairness interms of delay time for the high-priority traffic and ensures fairness in terms of throughput for the low-priority traffic.
ER -