The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문은 주로 광대역 이동 통신 애플리케이션을 목표로 프로토타입된 수축기 배열 재귀 최소 제곱(RLS) 프로세서의 개요를 제시합니다. RLS 알고리즘을 효과적으로 실행하기 위해 이 프로세서는 행렬 대수학에서 병렬 파이프라인 처리를 위한 QR 분해로 알려진 직교 삼각화 기술을 사용합니다. 프로세서 보드는 각각 약 백만 개의 게이트가 있는 19개의 애플리케이션별 집적 회로 칩으로 구성됩니다. 500비트 고정 소수점 신호 처리는 프로세서에서 이루어지며, 내부 셀 신호 처리의 한 주기에는 약 80nsec가 필요하고 경계 셀 신호 처리에는 약 10nsec가 필요합니다. 프로세서 보드는 최대 35개의 매개변수를 추정할 수 있습니다. 10개의 알려진 기호를 사용하여 41개의 매개변수를 추정하는 데 약 XNUMXμs가 소요됩니다. 프로토타입 시스톨릭 어레이 프로세서 보드의 신호 처리 성능을 평가하기 위해 프로토타입 보드를 사용하여 특정 개수의 매개변수를 추정하는 데 필요한 처리 시간을 디지털 신호 처리(DSP) 보드를 사용한 것과 비교했습니다. DSP 보드는 RLS 알고리즘의 표준 형식을 수행했습니다. 또한 복잡한 베이스밴드 페이딩/어레이 응답 시뮬레이터를 사용하여 최소 평균 제곱 오차 적응형 어레이 실험실 내 실험을 수행했습니다. 매개변수 추정 정확도 측면에서 프로세서는 부동 소수점 연산을 사용하는 기존 소프트웨어 엔진과 거의 동일한 결과를 생성하는 것으로 나타났습니다.
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Takahiro ASAI, Tadashi MATSUMOTO, "A Systolic Array RLS Processor" in IEICE TRANSACTIONS on Communications,
vol. E84-B, no. 5, pp. 1356-1361, May 2001, doi: .
Abstract: This paper presents the outline of the systolic array recursive least-squares (RLS) processor prototyped primarily with the aim of broadband mobile communication applications. To execute the RLS algorithm effectively, this processor uses an orthogonal triangularization technique known in matrix algebra as QR decomposition for parallel pipelined processing. The processor board comprises 19 application-specific integrated circuit chips, each with approximately one million gates. Thirty-two bit fixed-point signal processing takes place in the processor, with which one cycle of internal cell signal processing requires approximately 500 nsec, and boundary cell signal processing requires approximately 80 nsec. The processor board can estimate up to 10 parameters. It takes approximately 35 µs to estimate 10 parameters using 41 known symbols. To evaluate signal processing performance of the prototyped systolic array processor board, processing time required to estimate a certain number of parameters using the prototyped board was comapred with using a digital signal processing (DSP) board. The DSP board performed a standard form of the RLS algorithm. Additionally, we conducted minimum mean-squared error adaptive array in-lab experiments using a complex baseband fading/array response simulator. In terms of parameter estimation accuracy, the processor is found to produce virtually the same results as a conventional software engine using floating-point operations.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e84-b_5_1356/_p
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@ARTICLE{e84-b_5_1356,
author={Takahiro ASAI, Tadashi MATSUMOTO, },
journal={IEICE TRANSACTIONS on Communications},
title={A Systolic Array RLS Processor},
year={2001},
volume={E84-B},
number={5},
pages={1356-1361},
abstract={This paper presents the outline of the systolic array recursive least-squares (RLS) processor prototyped primarily with the aim of broadband mobile communication applications. To execute the RLS algorithm effectively, this processor uses an orthogonal triangularization technique known in matrix algebra as QR decomposition for parallel pipelined processing. The processor board comprises 19 application-specific integrated circuit chips, each with approximately one million gates. Thirty-two bit fixed-point signal processing takes place in the processor, with which one cycle of internal cell signal processing requires approximately 500 nsec, and boundary cell signal processing requires approximately 80 nsec. The processor board can estimate up to 10 parameters. It takes approximately 35 µs to estimate 10 parameters using 41 known symbols. To evaluate signal processing performance of the prototyped systolic array processor board, processing time required to estimate a certain number of parameters using the prototyped board was comapred with using a digital signal processing (DSP) board. The DSP board performed a standard form of the RLS algorithm. Additionally, we conducted minimum mean-squared error adaptive array in-lab experiments using a complex baseband fading/array response simulator. In terms of parameter estimation accuracy, the processor is found to produce virtually the same results as a conventional software engine using floating-point operations.},
keywords={},
doi={},
ISSN={},
month={May},}
부
TY - JOUR
TI - A Systolic Array RLS Processor
T2 - IEICE TRANSACTIONS on Communications
SP - 1356
EP - 1361
AU - Takahiro ASAI
AU - Tadashi MATSUMOTO
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E84-B
IS - 5
JA - IEICE TRANSACTIONS on Communications
Y1 - May 2001
AB - This paper presents the outline of the systolic array recursive least-squares (RLS) processor prototyped primarily with the aim of broadband mobile communication applications. To execute the RLS algorithm effectively, this processor uses an orthogonal triangularization technique known in matrix algebra as QR decomposition for parallel pipelined processing. The processor board comprises 19 application-specific integrated circuit chips, each with approximately one million gates. Thirty-two bit fixed-point signal processing takes place in the processor, with which one cycle of internal cell signal processing requires approximately 500 nsec, and boundary cell signal processing requires approximately 80 nsec. The processor board can estimate up to 10 parameters. It takes approximately 35 µs to estimate 10 parameters using 41 known symbols. To evaluate signal processing performance of the prototyped systolic array processor board, processing time required to estimate a certain number of parameters using the prototyped board was comapred with using a digital signal processing (DSP) board. The DSP board performed a standard form of the RLS algorithm. Additionally, we conducted minimum mean-squared error adaptive array in-lab experiments using a complex baseband fading/array response simulator. In terms of parameter estimation accuracy, the processor is found to produce virtually the same results as a conventional software engine using floating-point operations.
ER -