The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
다양한 구현 방법 지도 디코더 이 논문에서 제안되었습니다. 소설을 활용하다 파이프라인 구조의 시간 공유 프로세스, 저자는 상태 메트릭에 대한 재귀 프로세스에 의해 부과된 제한과 지도 디코더 정도의 수준으로 줄일 수 있습니다. SOVA(소프트 출력 Viterbi 알고리즘) 디코더. 또한, 저자들은 cdma-2000과 같은 가변 프레임 크기 시스템에 사용할 수 있는 효율적인 컨트롤러 구조를 제안합니다. 그만큼 지도 디코더 를 사용하여 블록 단위 여기서 설계된 알고리즘은 단 하나의 20,000 게이트 회로에만 구현되었습니다. 에 의해 검증되었습니다. VHDL, 이를 초기 시뮬레이션(C 프로그램)의 결과와 비교하였다. 디코더는 모든 하드웨어 환경을 고려하더라도 이상적인 MAP 디코더보다 약 300~8dB 더 큰 편차로 FPGA 회로에서 0.1회 반복을 통해 0.2kbps 디코딩 처리 능력을 보여주었습니다.
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Goo-Hyun PARK, Suk-Hyon YOON, Daesik HONG, Chang-Eon KANG, "Design for a Turbo-Code Decoder Using a Block-Wise Algorithm" in IEICE TRANSACTIONS on Communications,
vol. E85-B, no. 2, pp. 559-564, February 2002, doi: .
Abstract: Several implementation methods for a MAP decoder are proposed in this paper. Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursion process on state metrics, and the complexity of the MAP decoder can be reduced to a level on the order of a SOVA (Soft Output Viterbi Algorithm) decoder. In addition, the authors propose an efficient controller structure that can be used for variable frame-size systems such as cdma-2000. The MAP decoder using a block-wise algorithm designed here was implemented in only one 20,000 gate circuit. It was validated by VHDL, which was compared with the results of the initial simulation (C programs). The decoder demonstrated a 300 kbps decoding processing ability with 8 iterations on a FPGA circuit, with a deviation only about 0.1-0.2 dB greater than that for an ideal MAP decoder, even when all hardware environments are considered.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e85-b_2_559/_p
부
@ARTICLE{e85-b_2_559,
author={Goo-Hyun PARK, Suk-Hyon YOON, Daesik HONG, Chang-Eon KANG, },
journal={IEICE TRANSACTIONS on Communications},
title={Design for a Turbo-Code Decoder Using a Block-Wise Algorithm},
year={2002},
volume={E85-B},
number={2},
pages={559-564},
abstract={Several implementation methods for a MAP decoder are proposed in this paper. Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursion process on state metrics, and the complexity of the MAP decoder can be reduced to a level on the order of a SOVA (Soft Output Viterbi Algorithm) decoder. In addition, the authors propose an efficient controller structure that can be used for variable frame-size systems such as cdma-2000. The MAP decoder using a block-wise algorithm designed here was implemented in only one 20,000 gate circuit. It was validated by VHDL, which was compared with the results of the initial simulation (C programs). The decoder demonstrated a 300 kbps decoding processing ability with 8 iterations on a FPGA circuit, with a deviation only about 0.1-0.2 dB greater than that for an ideal MAP decoder, even when all hardware environments are considered.},
keywords={},
doi={},
ISSN={},
month={February},}
부
TY - JOUR
TI - Design for a Turbo-Code Decoder Using a Block-Wise Algorithm
T2 - IEICE TRANSACTIONS on Communications
SP - 559
EP - 564
AU - Goo-Hyun PARK
AU - Suk-Hyon YOON
AU - Daesik HONG
AU - Chang-Eon KANG
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E85-B
IS - 2
JA - IEICE TRANSACTIONS on Communications
Y1 - February 2002
AB - Several implementation methods for a MAP decoder are proposed in this paper. Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursion process on state metrics, and the complexity of the MAP decoder can be reduced to a level on the order of a SOVA (Soft Output Viterbi Algorithm) decoder. In addition, the authors propose an efficient controller structure that can be used for variable frame-size systems such as cdma-2000. The MAP decoder using a block-wise algorithm designed here was implemented in only one 20,000 gate circuit. It was validated by VHDL, which was compared with the results of the initial simulation (C programs). The decoder demonstrated a 300 kbps decoding processing ability with 8 iterations on a FPGA circuit, with a deviation only about 0.1-0.2 dB greater than that for an ideal MAP decoder, even when all hardware environments are considered.
ER -