The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 편지에서는 소수의 요소로 구성된 12.5비트 디지털 위상 배열의 사이드로브 레벨을 조사합니다. 위상 배열에 적용할 수 있는 여러 위상 천이기 설계 중 13.2비트 설계는 회로 요소 수가 가장 적기 때문에 개발 및 제조 비용이 가장 저렴합니다. 이제 다음과 같은 질문이 생깁니다. 0비트 위상 배열이 실용적입니까? 사이드로브 레벨을 얼마나 낮출 수 있습니까? 질문에 대답하기 위해 등방성 요소의 균일하게 여기된 선형 배열의 사이드로브 수준을 줄이기 위해 세 가지 방법이 시도되었습니다. 방법에는 48차 위상 공급 방법, 주기적인 위상 오류의 부분 무작위화 방법 및 유전 알고리즘(GA) 접근 방식이 있습니다. 방법 중 21차 위상 피드 방법은 11.2개 요소, 반파장 간격 배열에 대해 13.0~0도의 조향 각도에서 -30dB - -11dB 부근의 가장 낮은 사이드로브 레벨을 제공하고, -0.6dB - - XNUMX개 요소, XNUMX파장 간격 배열의 경우 조향 각도가 XNUMX~XNUMX도에서 XNUMXdB입니다. 시스템 요구 사항에 따라 다르지만 이러한 값은 일부 애플리케이션에서 허용될 수 있으므로 적절하게 설계된 XNUMX비트 위상 배열이 실제 시스템에서 실용적일 수 있습니다.
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Masaharu FUJITA, "Sidelobe Level of a Two-Bit Digital Phased Array Composed of a Small Number of Elements" in IEICE TRANSACTIONS on Communications,
vol. E85-B, no. 5, pp. 982-986, May 2002, doi: .
Abstract: This letter investigates sidelobe levels of a two-bit digital phased array composed of a small number of elements. Among several phase shifter designs applicable to phased arrays, a two-bit design needs the least number of circuit elements so that the development and manufacturing need the lowest cost. Now the following questions arise. Is a two-bit phased array practical? How low can its sidelobe level be reduced? To answer the questions, three methods are tried to reduce the sidelobe level of a uniformly-excited linear array of isotropic elements. The methods are the quadratic-phase feed method, the partially randomizing method of periodic phase errors, and the genetic algorithm (GA) approach. Among the methods, the quadratic-phase feed method provides the lowest sidelobe level around -12.5 dB - -13.2 dB in the steering angles from 0 to 48 degrees for a 21-element, half-wavelength spacing array, and -11.2 dB - -13.0 dB in the steering angles from 0 to 30 degrees for an 11-element, 0.6-wavelength spacing array. Although it depends on the system requirement, these values would be acceptable in some applications, hence a two-bit phased array designed properly may be practical in an actual system.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e85-b_5_982/_p
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@ARTICLE{e85-b_5_982,
author={Masaharu FUJITA, },
journal={IEICE TRANSACTIONS on Communications},
title={Sidelobe Level of a Two-Bit Digital Phased Array Composed of a Small Number of Elements},
year={2002},
volume={E85-B},
number={5},
pages={982-986},
abstract={This letter investigates sidelobe levels of a two-bit digital phased array composed of a small number of elements. Among several phase shifter designs applicable to phased arrays, a two-bit design needs the least number of circuit elements so that the development and manufacturing need the lowest cost. Now the following questions arise. Is a two-bit phased array practical? How low can its sidelobe level be reduced? To answer the questions, three methods are tried to reduce the sidelobe level of a uniformly-excited linear array of isotropic elements. The methods are the quadratic-phase feed method, the partially randomizing method of periodic phase errors, and the genetic algorithm (GA) approach. Among the methods, the quadratic-phase feed method provides the lowest sidelobe level around -12.5 dB - -13.2 dB in the steering angles from 0 to 48 degrees for a 21-element, half-wavelength spacing array, and -11.2 dB - -13.0 dB in the steering angles from 0 to 30 degrees for an 11-element, 0.6-wavelength spacing array. Although it depends on the system requirement, these values would be acceptable in some applications, hence a two-bit phased array designed properly may be practical in an actual system.},
keywords={},
doi={},
ISSN={},
month={May},}
부
TY - JOUR
TI - Sidelobe Level of a Two-Bit Digital Phased Array Composed of a Small Number of Elements
T2 - IEICE TRANSACTIONS on Communications
SP - 982
EP - 986
AU - Masaharu FUJITA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E85-B
IS - 5
JA - IEICE TRANSACTIONS on Communications
Y1 - May 2002
AB - This letter investigates sidelobe levels of a two-bit digital phased array composed of a small number of elements. Among several phase shifter designs applicable to phased arrays, a two-bit design needs the least number of circuit elements so that the development and manufacturing need the lowest cost. Now the following questions arise. Is a two-bit phased array practical? How low can its sidelobe level be reduced? To answer the questions, three methods are tried to reduce the sidelobe level of a uniformly-excited linear array of isotropic elements. The methods are the quadratic-phase feed method, the partially randomizing method of periodic phase errors, and the genetic algorithm (GA) approach. Among the methods, the quadratic-phase feed method provides the lowest sidelobe level around -12.5 dB - -13.2 dB in the steering angles from 0 to 48 degrees for a 21-element, half-wavelength spacing array, and -11.2 dB - -13.0 dB in the steering angles from 0 to 30 degrees for an 11-element, 0.6-wavelength spacing array. Although it depends on the system requirement, these values would be acceptable in some applications, hence a two-bit phased array designed properly may be practical in an actual system.
ER -