The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
MPLS(Multi-Protocol Label Switching) 네트워크 도메인에서 비동기 전송 모드-ATM-LSR(레이블 스위치 라우터)은 최고의 전달 기능을 제공하는 데 가장 적합한 후보로 간주됩니다. ATM-LSR은 많은 IP 경로를 동일한 VPI/VCI 레이블에 매핑하여 확장성을 지원하는 VC 병합 방식을 구현합니다. VC 병합에는 분할되었지만 인터리빙된 AAL-5 셀에서 원본 패킷을 재구성하기 위해 재조립 버퍼가 필요합니다. 본 논문에서는 부분적인 VC 병합 기능을 갖춘 ATM-LSR의 성능을 분석하고 VC 병합이 재조립 및 출력 버퍼 요구 사항에 미치는 영향을 조사합니다. 수학적 분석의 수치 계산 복잡성은 다음과 같이 줄일 수 있습니다. O(M4)에 O(M2), 어디서 M ON-OFF 소스의 총 개수입니다. 우리는 또한 출력 버퍼의 분포를 만족스러운 정확도로 근사화하는 폐쇄형 방정식을 제안합니다. 수치 결과에 따르면 들어오는 셀이 심하게 인터리브될 때 VC 병합에서는 무시할 수 없는 출력 버퍼 크기와 동일한 차수의 리어셈블리 버퍼 크기가 필요하다는 것을 보여줍니다.
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Po-Chou LIN, Chung-Ju CHANG, "Analysis of Buffer Requirement for ATM-LSRs with Partial VC-Merging Capability" in IEICE TRANSACTIONS on Communications,
vol. E85-B, no. 6, pp. 1115-1123, June 2002, doi: .
Abstract: In an Multi-Protocol Label Switching (MPLS) network domain, Asynchronous Transfer Mode--Label Switch Routers (ATM-LSRs) are considered the best candidate for providing the highest forwarding capability. ATM-LSRs implement a VC-merging scheme that allows many IP routes to be mapped into the same VPI/VCI label, hence supporting scalability. The VC-merging requires reassembly buffers to reconstruct an original packet from its segmented but interleaved AAL-5 cells. In this paper, we analyze the performance of an ATM-LSR with partial VC-merging capability and investigate the impact of VC-merging on the requirement of the reassembly and output buffer. The numerical computation complexity of the mathematical analysis can be reduced from O(M4) to O(M2), where M is the total number of ON-OFF sources. We also propose a closed-form equation, which approximates the distribution of the output buffer with satisfactory accuracy. Numerical results show that when incoming cells are severely interleaved, the VC-merging needs the reassembly buffer size to be of the same order as the output buffer size, which cannot be ignored.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e85-b_6_1115/_p
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@ARTICLE{e85-b_6_1115,
author={Po-Chou LIN, Chung-Ju CHANG, },
journal={IEICE TRANSACTIONS on Communications},
title={Analysis of Buffer Requirement for ATM-LSRs with Partial VC-Merging Capability},
year={2002},
volume={E85-B},
number={6},
pages={1115-1123},
abstract={In an Multi-Protocol Label Switching (MPLS) network domain, Asynchronous Transfer Mode--Label Switch Routers (ATM-LSRs) are considered the best candidate for providing the highest forwarding capability. ATM-LSRs implement a VC-merging scheme that allows many IP routes to be mapped into the same VPI/VCI label, hence supporting scalability. The VC-merging requires reassembly buffers to reconstruct an original packet from its segmented but interleaved AAL-5 cells. In this paper, we analyze the performance of an ATM-LSR with partial VC-merging capability and investigate the impact of VC-merging on the requirement of the reassembly and output buffer. The numerical computation complexity of the mathematical analysis can be reduced from O(M4) to O(M2), where M is the total number of ON-OFF sources. We also propose a closed-form equation, which approximates the distribution of the output buffer with satisfactory accuracy. Numerical results show that when incoming cells are severely interleaved, the VC-merging needs the reassembly buffer size to be of the same order as the output buffer size, which cannot be ignored.},
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - Analysis of Buffer Requirement for ATM-LSRs with Partial VC-Merging Capability
T2 - IEICE TRANSACTIONS on Communications
SP - 1115
EP - 1123
AU - Po-Chou LIN
AU - Chung-Ju CHANG
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E85-B
IS - 6
JA - IEICE TRANSACTIONS on Communications
Y1 - June 2002
AB - In an Multi-Protocol Label Switching (MPLS) network domain, Asynchronous Transfer Mode--Label Switch Routers (ATM-LSRs) are considered the best candidate for providing the highest forwarding capability. ATM-LSRs implement a VC-merging scheme that allows many IP routes to be mapped into the same VPI/VCI label, hence supporting scalability. The VC-merging requires reassembly buffers to reconstruct an original packet from its segmented but interleaved AAL-5 cells. In this paper, we analyze the performance of an ATM-LSR with partial VC-merging capability and investigate the impact of VC-merging on the requirement of the reassembly and output buffer. The numerical computation complexity of the mathematical analysis can be reduced from O(M4) to O(M2), where M is the total number of ON-OFF sources. We also propose a closed-form equation, which approximates the distribution of the output buffer with satisfactory accuracy. Numerical results show that when incoming cells are severely interleaved, the VC-merging needs the reassembly buffer size to be of the same order as the output buffer size, which cannot be ignored.
ER -