The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
클라우드 컴퓨팅을 기반으로 한 고급 정보 처리 서비스에 대한 수요가 높습니다. 그러나 사용자는 자신의 목적에 맞게 클라우드 서비스를 사용자 정의할 수 있기를 원합니다. 각 사용자의 목적에 최적화된 영상 처리 서비스를 제공하기 위해 CPU-FPGA(Field Programmable Gate Array) 결합 서버 아키텍처에서 영상 처리 기능을 체인화하는 기술을 제안한다. 네트워크에서 여러 이미지 처리 기능을 결합하기 위한 가장 중요한 요구 사항 중 하나는 서버 노드의 대기 시간이 짧다는 것입니다. 그러나 기존 CPU-FPGA 아키텍처에서는 애플리케이션 수준에서 CPU와 FPGA 간의 이미지 처리 및 데이터 전송의 정확성을 보장하기 위한 패킷 재정렬의 오버헤드로 인해 큰 지연이 발생합니다. 본 논문에서는 저지연 이미지 처리를 위한 실시간 패킷 재정렬 회로를 갖춘 CPU-FPGA 서버 아키텍처를 제시합니다. 우리 아이디어의 효율성을 확인하기 위해 오프로드된 이미지 처리 기능으로 HOG(Histogram of Oriented Gradients) 기능 계산의 대기 시간을 평가했습니다. 그 결과 기존 CPU-FPGA 아키텍처에 비해 지연 시간이 약 26배 낮은 것으로 나타났다. 또한 3.7Gbps 입력 속도에서 패킷의 90%가 무작위로 교환되는 최악의 조건에서 처리량은 40% 미만으로 감소했습니다. 마지막으로 우리의 아키텍처를 이용하여 영상처리 기능을 결합하여 실시간 영상 모니터링 서비스를 제공할 수 있음을 시연하였다.
Yuta UKON
NTT Corporation
Koji YAMAZAKI
NTT Corporation
Koyo NITTA
NTT Corporation
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Yuta UKON, Koji YAMAZAKI, Koyo NITTA, "Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture" in IEICE TRANSACTIONS on Communications,
vol. E103-B, no. 1, pp. 11-19, January 2020, doi: 10.1587/transcom.2019CPP0001.
Abstract: Advanced information-processing services based on cloud computing are in great demand. However, users want to be able to customize cloud services for their own purposes. To provide image-processing services that can be optimized for the purpose of each user, we propose a technique for chaining image-processing functions in a CPU-field programmable gate array (FPGA) coupled server architecture. One of the most important requirements for combining multiple image-processing functions on a network, is low latency in server nodes. However, large delay occurs in the conventional CPU-FPGA architecture due to the overheads of packet reordering for ensuring the correctness of image processing and data transfer between the CPU and FPGA at the application level. This paper presents a CPU-FPGA server architecture with a real-time packet reordering circuit for low-latency image processing. In order to confirm the efficiency of our idea, we evaluated the latency of histogram of oriented gradients (HOG) feature calculation as an offloaded image-processing function. The results show that the latency is about 26 times lower than that of the conventional CPU-FPGA architecture. Moreover, the throughput decreased by less than 3.7% under the worst-case condition where 90 percent of the packets are randomly swapped at a 40-Gbps input rate. Finally, we demonstrated that a real-time video monitoring service can be provided by combining image processing functions using our architecture.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.2019CPP0001/_p
부
@ARTICLE{e103-b_1_11,
author={Yuta UKON, Koji YAMAZAKI, Koyo NITTA, },
journal={IEICE TRANSACTIONS on Communications},
title={Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture},
year={2020},
volume={E103-B},
number={1},
pages={11-19},
abstract={Advanced information-processing services based on cloud computing are in great demand. However, users want to be able to customize cloud services for their own purposes. To provide image-processing services that can be optimized for the purpose of each user, we propose a technique for chaining image-processing functions in a CPU-field programmable gate array (FPGA) coupled server architecture. One of the most important requirements for combining multiple image-processing functions on a network, is low latency in server nodes. However, large delay occurs in the conventional CPU-FPGA architecture due to the overheads of packet reordering for ensuring the correctness of image processing and data transfer between the CPU and FPGA at the application level. This paper presents a CPU-FPGA server architecture with a real-time packet reordering circuit for low-latency image processing. In order to confirm the efficiency of our idea, we evaluated the latency of histogram of oriented gradients (HOG) feature calculation as an offloaded image-processing function. The results show that the latency is about 26 times lower than that of the conventional CPU-FPGA architecture. Moreover, the throughput decreased by less than 3.7% under the worst-case condition where 90 percent of the packets are randomly swapped at a 40-Gbps input rate. Finally, we demonstrated that a real-time video monitoring service can be provided by combining image processing functions using our architecture.},
keywords={},
doi={10.1587/transcom.2019CPP0001},
ISSN={1745-1345},
month={January},}
부
TY - JOUR
TI - Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture
T2 - IEICE TRANSACTIONS on Communications
SP - 11
EP - 19
AU - Yuta UKON
AU - Koji YAMAZAKI
AU - Koyo NITTA
PY - 2020
DO - 10.1587/transcom.2019CPP0001
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E103-B
IS - 1
JA - IEICE TRANSACTIONS on Communications
Y1 - January 2020
AB - Advanced information-processing services based on cloud computing are in great demand. However, users want to be able to customize cloud services for their own purposes. To provide image-processing services that can be optimized for the purpose of each user, we propose a technique for chaining image-processing functions in a CPU-field programmable gate array (FPGA) coupled server architecture. One of the most important requirements for combining multiple image-processing functions on a network, is low latency in server nodes. However, large delay occurs in the conventional CPU-FPGA architecture due to the overheads of packet reordering for ensuring the correctness of image processing and data transfer between the CPU and FPGA at the application level. This paper presents a CPU-FPGA server architecture with a real-time packet reordering circuit for low-latency image processing. In order to confirm the efficiency of our idea, we evaluated the latency of histogram of oriented gradients (HOG) feature calculation as an offloaded image-processing function. The results show that the latency is about 26 times lower than that of the conventional CPU-FPGA architecture. Moreover, the throughput decreased by less than 3.7% under the worst-case condition where 90 percent of the packets are randomly swapped at a 40-Gbps input rate. Finally, we demonstrated that a real-time video monitoring service can be provided by combining image processing functions using our architecture.
ER -