The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
비용 효율적인 액세스 네트워크 시스템 구축을 위해 PON(Passive Optical Network)에 NFV(네트워크 기능 가상화) 및 SDN(소프트웨어 정의 네트워킹)을 적용하는 것이 주목받고 있습니다. 본 논문에서는 OLT(Optical Line Terminal)의 프로토콜 처리를 위한 하드웨어 가속기로서 P-FSM(Programmable Finite State Machine)의 새로운 아키텍처를 제시합니다. P-FSM은 다양한 유형의 FSM을 관리하여 OLT의 유연성을 향상시키고 전체 칩 영역을 무시할 만큼 증가시키면서 유선 속도 성능을 달성하는 프로그래밍 가능 하드웨어입니다. P-FSM은 논리 영역을 최소화하기 위한 통신 프로토콜의 상태 관리를 위한 특정 아키텍처, 프로그램 메모리를 최소화하기 위한 메모리 분산 구현, 메모리 영역을 최소화하고 처리 시간을 줄이기 위한 새로운 분기 작업이라는 세 가지 핵심 기술을 사용하여 구현됩니다. . 평가 결과에 따르면 P-FSM은 유선 속도 성능을 달성하면서 동일한 아키텍처에서 10G-EPON/NG-PON2 통신 프로토콜을 처리할 수 있는 것으로 나타났습니다. 전체 설계 면적의 증가는 유연성이 없는 기존 통신 SoC 면적에 비해 지원되는 프로토콜 수에 따라 1.5~4.9%에 불과하다. 또한 우리 아키텍처는 시스템 규모에 따라 FSM 수와 최대 ONU 연결 수를 수정하는 데 필요한 확장성을 갖추고 있음을 분명히 합니다.
Saki HATTA
NTT Corporation
Nobuyuki TANAKA
NTT Corporation
Hiroyuki UZAWA
NTT Corporation
Koyo NITTA
NTT Corporation
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부
Saki HATTA, Nobuyuki TANAKA, Hiroyuki UZAWA, Koyo NITTA, "Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems" in IEICE TRANSACTIONS on Communications,
vol. E104-B, no. 3, pp. 277-285, March 2021, doi: 10.1587/transcom.2020EBP3050.
Abstract: The application of network function virtualization (NFV) and software-defined networking (SDN) to passive optical networks (PONs) is attracting attention for the deployment of cost-effective access network systems. This paper presents a novel architecture of a programmable finite state machine (P-FSM) as a hardware accelerator for protocol processing in an optical line terminal (OLT). The P-FSM is programmable hardware that manages various types of FSMs to enhance flexibility in OLTs and achieve wired-rate performance with a negligible increase in total chip area. The P-FSM is implemented using three key technologies: a specific architecture for state management of communications protocols to minimize the logic area, a memory distributed implementation to minimize the program memory, and a new branch operation to minimize the memory area and reduce processing time. Evaluation results show that the P-FSM can handle 10G-EPON/NG-PON2 communications protocols in the same architecture while achieving wired-rate performance. The increase in the total designed area is only 1.5% to 4.9% depending on the number of protocols supported compared to the area of a conventional communications SoC without flexibility. We also clarify that our architecture has the scalability needed to modify the number of FSMs and the maximum number of ONU connections according to the system scale.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.2020EBP3050/_p
부
@ARTICLE{e104-b_3_277,
author={Saki HATTA, Nobuyuki TANAKA, Hiroyuki UZAWA, Koyo NITTA, },
journal={IEICE TRANSACTIONS on Communications},
title={Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems},
year={2021},
volume={E104-B},
number={3},
pages={277-285},
abstract={The application of network function virtualization (NFV) and software-defined networking (SDN) to passive optical networks (PONs) is attracting attention for the deployment of cost-effective access network systems. This paper presents a novel architecture of a programmable finite state machine (P-FSM) as a hardware accelerator for protocol processing in an optical line terminal (OLT). The P-FSM is programmable hardware that manages various types of FSMs to enhance flexibility in OLTs and achieve wired-rate performance with a negligible increase in total chip area. The P-FSM is implemented using three key technologies: a specific architecture for state management of communications protocols to minimize the logic area, a memory distributed implementation to minimize the program memory, and a new branch operation to minimize the memory area and reduce processing time. Evaluation results show that the P-FSM can handle 10G-EPON/NG-PON2 communications protocols in the same architecture while achieving wired-rate performance. The increase in the total designed area is only 1.5% to 4.9% depending on the number of protocols supported compared to the area of a conventional communications SoC without flexibility. We also clarify that our architecture has the scalability needed to modify the number of FSMs and the maximum number of ONU connections according to the system scale.},
keywords={},
doi={10.1587/transcom.2020EBP3050},
ISSN={1745-1345},
month={March},}
부
TY - JOUR
TI - Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems
T2 - IEICE TRANSACTIONS on Communications
SP - 277
EP - 285
AU - Saki HATTA
AU - Nobuyuki TANAKA
AU - Hiroyuki UZAWA
AU - Koyo NITTA
PY - 2021
DO - 10.1587/transcom.2020EBP3050
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E104-B
IS - 3
JA - IEICE TRANSACTIONS on Communications
Y1 - March 2021
AB - The application of network function virtualization (NFV) and software-defined networking (SDN) to passive optical networks (PONs) is attracting attention for the deployment of cost-effective access network systems. This paper presents a novel architecture of a programmable finite state machine (P-FSM) as a hardware accelerator for protocol processing in an optical line terminal (OLT). The P-FSM is programmable hardware that manages various types of FSMs to enhance flexibility in OLTs and achieve wired-rate performance with a negligible increase in total chip area. The P-FSM is implemented using three key technologies: a specific architecture for state management of communications protocols to minimize the logic area, a memory distributed implementation to minimize the program memory, and a new branch operation to minimize the memory area and reduce processing time. Evaluation results show that the P-FSM can handle 10G-EPON/NG-PON2 communications protocols in the same architecture while achieving wired-rate performance. The increase in the total designed area is only 1.5% to 4.9% depending on the number of protocols supported compared to the area of a conventional communications SoC without flexibility. We also clarify that our architecture has the scalability needed to modify the number of FSMs and the maximum number of ONU connections according to the system scale.
ER -