The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 엄격한 채널 액세스를 준수하면서 버스트 데이터 전송을 위한 이론적인 MAC 처리량에 가까운 효율적인 IEEE 802.11e 기반 하드웨어/소프트웨어 공동 설계 매체 액세스 제어(MAC) 시스템 아키텍처를 구현하는 빠르고 체계적인 아키텍처 탐색 방법을 제시합니다. 시간 요구 사항. 우리의 설계 접근 방식은 SystemC 기반 TLM(트랜잭션 수준 모델링) 프레임워크를 사용하여 재구성 가능한 범용 컴퓨팅 및 통신 리소스를 애플리케이션 모델에 통합하여 핵심 매개변수, 시스템 성능 및 애플리케이션별 최적화를 신속하게 평가합니다. 그 결과, 100Mbps의 PHY(물리계층) 데이터 속도로 전송 시 260Mbps 이상의 시뮬레이션된 MAC 처리량을 달성하는 MAC 시스템 아키텍처가 얻어졌습니다. 이 결과는 Xilinx FPGA(Field-Programmable Gate Array) 보드에서 XX-IMPLEMENTATION을 통해 검증되었습니다.
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부
Sung-Rok YOON, Min Li HUANG, Sangho SEO, Hiroshi OCHI, Sin-Chong PARK, "A Fast Architecture Exploration Method for High Throughput IEEE 802.11e MAC Implementation Using SystemC" in IEICE TRANSACTIONS on Communications,
vol. E93-B, no. 10, pp. 2833-2836, October 2010, doi: 10.1587/transcom.E93.B.2833.
Abstract: This paper presents a fast and systematic architecture exploration method that realizes an efficient IEEE 802.11e based hardware/software co-design Medium Access Control (MAC) system architecture, which can achieve near theoretical MAC throughput for burst data transmission while complying with strict channel access time requirements. Our design approach uses SystemC based Transaction Level Modeling (TLM) framework to integrate reconfigurable general purpose computing and communication resources into the application model for rapid evaluation of core parameters, system performance, and application specific optimizations. As a result, a MAC system architecture that achieves a simulated MAC throughput of more than 100 Mbps when transmitted at 260 Mbps of Physical Layer (PHY) data rate is obtained. This result is verified with X-X-IMPLEMENTATION on a Xilinx Field-Programmable Gate Array (FPGA) board.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.E93.B.2833/_p
부
@ARTICLE{e93-b_10_2833,
author={Sung-Rok YOON, Min Li HUANG, Sangho SEO, Hiroshi OCHI, Sin-Chong PARK, },
journal={IEICE TRANSACTIONS on Communications},
title={A Fast Architecture Exploration Method for High Throughput IEEE 802.11e MAC Implementation Using SystemC},
year={2010},
volume={E93-B},
number={10},
pages={2833-2836},
abstract={This paper presents a fast and systematic architecture exploration method that realizes an efficient IEEE 802.11e based hardware/software co-design Medium Access Control (MAC) system architecture, which can achieve near theoretical MAC throughput for burst data transmission while complying with strict channel access time requirements. Our design approach uses SystemC based Transaction Level Modeling (TLM) framework to integrate reconfigurable general purpose computing and communication resources into the application model for rapid evaluation of core parameters, system performance, and application specific optimizations. As a result, a MAC system architecture that achieves a simulated MAC throughput of more than 100 Mbps when transmitted at 260 Mbps of Physical Layer (PHY) data rate is obtained. This result is verified with X-X-IMPLEMENTATION on a Xilinx Field-Programmable Gate Array (FPGA) board.},
keywords={},
doi={10.1587/transcom.E93.B.2833},
ISSN={1745-1345},
month={October},}
부
TY - JOUR
TI - A Fast Architecture Exploration Method for High Throughput IEEE 802.11e MAC Implementation Using SystemC
T2 - IEICE TRANSACTIONS on Communications
SP - 2833
EP - 2836
AU - Sung-Rok YOON
AU - Min Li HUANG
AU - Sangho SEO
AU - Hiroshi OCHI
AU - Sin-Chong PARK
PY - 2010
DO - 10.1587/transcom.E93.B.2833
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E93-B
IS - 10
JA - IEICE TRANSACTIONS on Communications
Y1 - October 2010
AB - This paper presents a fast and systematic architecture exploration method that realizes an efficient IEEE 802.11e based hardware/software co-design Medium Access Control (MAC) system architecture, which can achieve near theoretical MAC throughput for burst data transmission while complying with strict channel access time requirements. Our design approach uses SystemC based Transaction Level Modeling (TLM) framework to integrate reconfigurable general purpose computing and communication resources into the application model for rapid evaluation of core parameters, system performance, and application specific optimizations. As a result, a MAC system architecture that achieves a simulated MAC throughput of more than 100 Mbps when transmitted at 260 Mbps of Physical Layer (PHY) data rate is obtained. This result is verified with X-X-IMPLEMENTATION on a Xilinx Field-Programmable Gate Array (FPGA) board.
ER -