The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 편지에서는 새로운 고속 잠금 디지털 제어 위상 고정 루프(DCPLL)가 제안되었습니다. 이 DCPLL은 잠금 시간을 줄이기 위해 새로운 주파수 검색 알고리즘을 채택합니다. 또한 전력 소비를 줄이기 위해 주파수 분배기는 주파수 획득 중에 주파수 검출기로 재사용되고, 위상 획득 중에는 시간-디지털 변환기 모듈로 재사용됩니다. 제안된 알고리즘과 아키텍처를 검증하기 위해 SMIC 0.18 µm 1P6M CMOS 기술을 사용하여 DCPLL 설계를 구현했습니다. Spice 시뮬레이션 결과는 DCPLL이 3MHz로 고정될 때 11개의 기준 사이클에서 주파수 획득을 달성하고 200개의 기준 사이클에서 위상 획득을 완료할 수 있음을 보여줍니다. DCPLL의 해당 전력 소비는 3.71mW입니다.
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부
Xin CHEN, Jun YANG, Long-xing SHI, "A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 12, pp. 1971-1975, December 2008, doi: 10.1093/ietele/e91-c.12.1971.
Abstract: A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter module during the phase acquisition. To verify the proposed algorithm and architecture, a DCPLL design is implemented by SMIC 0.18 µm 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200 MHz. The corresponding power consumption of DCPLL is 3.71 mW.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.12.1971/_p
부
@ARTICLE{e91-c_12_1971,
author={Xin CHEN, Jun YANG, Long-xing SHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop},
year={2008},
volume={E91-C},
number={12},
pages={1971-1975},
abstract={A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter module during the phase acquisition. To verify the proposed algorithm and architecture, a DCPLL design is implemented by SMIC 0.18 µm 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200 MHz. The corresponding power consumption of DCPLL is 3.71 mW.},
keywords={},
doi={10.1093/ietele/e91-c.12.1971},
ISSN={1745-1353},
month={December},}
부
TY - JOUR
TI - A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop
T2 - IEICE TRANSACTIONS on Electronics
SP - 1971
EP - 1975
AU - Xin CHEN
AU - Jun YANG
AU - Long-xing SHI
PY - 2008
DO - 10.1093/ietele/e91-c.12.1971
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2008
AB - A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter module during the phase acquisition. To verify the proposed algorithm and architecture, a DCPLL design is implemented by SMIC 0.18 µm 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200 MHz. The corresponding power consumption of DCPLL is 3.71 mW.
ER -