The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 최적화된 BIST(Built-In Self-Test) 기술을 제안한다. 단일 입력 변경 회로의 구성을 표현하기 위해 단순화된 대수 모델이 개발되었습니다. 새로운 단일 입력 변경 시퀀스 생성 기술이 설계되었습니다. 이는 수정된 스캔 시프트 레지스터, 시드 저장 어레이 및 일련의 XOR 게이트로 구성됩니다. 이 회로는 더 고유한 벡터의 단일 입력 변경 시퀀스를 자동으로 생성할 수 있습니다. ISCAS-89 벤치마크를 기반으로 한 실험 결과는 제안된 방법이 테스트 애플리케이션 동안 낮은 스위칭 활동으로 높은 고착 결함 커버리지를 달성할 수 있음을 보여줍니다.
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부
Feng LIANG, ShaoChong LEI, ZhiBiao SHAO, "A Single Input Change Test Pattern Generator for Sequential Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 8, pp. 1365-1370, August 2008, doi: 10.1093/ietele/e91-c.8.1365.
Abstract: An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.8.1365/_p
부
@ARTICLE{e91-c_8_1365,
author={Feng LIANG, ShaoChong LEI, ZhiBiao SHAO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Single Input Change Test Pattern Generator for Sequential Circuits},
year={2008},
volume={E91-C},
number={8},
pages={1365-1370},
abstract={An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.},
keywords={},
doi={10.1093/ietele/e91-c.8.1365},
ISSN={1745-1353},
month={August},}
부
TY - JOUR
TI - A Single Input Change Test Pattern Generator for Sequential Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 1365
EP - 1370
AU - Feng LIANG
AU - ShaoChong LEI
AU - ZhiBiao SHAO
PY - 2008
DO - 10.1093/ietele/e91-c.8.1365
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2008
AB - An optimized Built-In Self-Test technology is proposed in this paper. A simplified algebraic model is developed to represent the configurations of single input change circuits. A novel single input change sequence generation technique is designed. It consists of a modified scan shift register, a seed storage array and a series of XOR gates. This circuitry can automatically generate single input change sequences of more unique vectors. Experimental results based on the ISCAS-89 benchmark show that the proposed method can achieve high stuck-at fault coverage with low switching activity during test applications.
ER -