The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Deep Submicron 반도체 기술은 필요한 설계 마진을 제공할 수 없기 때문에 최악의 설계를 불가능하게 만듭니다. 우리는 CTV(Constructive Timing Violation)라고 부르는 일반적인 사례 설계 방법론을 조사하고 있습니다. 이 문서에서는 CTV 개념을 확장하여 종속 명령을 축소하여 성능을 향상시킵니다. 상세한 시뮬레이션을 기반으로 우리는 제안된 메커니즘이 종속 명령어를 효과적으로 축소한다는 것을 발견했습니다.
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Toshinori SATO, "A Simple Mechanism for Collapsing Instructions under Timing Speculation" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1394-1401, September 2008, doi: 10.1093/ietele/e91-c.9.1394.
Abstract: The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement. Based on detailed simulations, we find the proposed mechanism effectively collapses dependent instructions.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1394/_p
부
@ARTICLE{e91-c_9_1394,
author={Toshinori SATO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Simple Mechanism for Collapsing Instructions under Timing Speculation},
year={2008},
volume={E91-C},
number={9},
pages={1394-1401},
abstract={The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement. Based on detailed simulations, we find the proposed mechanism effectively collapses dependent instructions.},
keywords={},
doi={10.1093/ietele/e91-c.9.1394},
ISSN={1745-1353},
month={September},}
부
TY - JOUR
TI - A Simple Mechanism for Collapsing Instructions under Timing Speculation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1394
EP - 1401
AU - Toshinori SATO
PY - 2008
DO - 10.1093/ietele/e91-c.9.1394
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement. Based on detailed simulations, we find the proposed mechanism effectively collapses dependent instructions.
ER -