The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 다목적 멀티미디어 프로세서를 구성하기 위한 CAM(Content Addressable Memory)과 대용량 병렬 메모리 내장 SIMD 매트릭스의 통합 아키텍처를 제시합니다. 대용량 병렬 메모리 내장형 SIMD 매트릭스는 2,048개의 2비트 처리 요소를 갖추고 있으며, 이는 유연한 스위칭 네트워크로 연결되며, 단일 명령으로 2비트 2,048방향 비트 직렬 및 워드 병렬 연산을 지원합니다. SIMD 매트릭스 아키텍처는 멀티미디어 애플리케이션에서 반복되는 산술 연산 유형을 처리하는 더 나은 방법으로 검증되었습니다. 본 문서에 보고된 제안된 아키텍처는 추가로 CAM 기술을 활용하므로 빠른 파이프라인 테이블 조회 코딩 작업이 가능합니다. 산술 및 테이블 조회 작업이 모두 매우 빠르게 실행되므로 제안된 새로운 아키텍처는 결과적으로 효율적이고 다양한 멀티미디어 데이터 처리를 실현할 수 있습니다. 자주 사용되는 JPEG 이미지 압축 애플리케이션의 예에 대해 제안된 CAM 강화 대규모 병렬 SIMD 매트릭스 프로세서의 평가 결과는 기존 모바일 DSP 아키텍처에 비해 필요한 클록 사이클 수를 86%까지 줄일 수 있음을 보여줍니다. Mpixel/mm 단위로 결정된 성능2 CAM이 없는 대용량 병렬 메모리 내장 SIMD 매트릭스 프로세서와 기존 모바일 DSP보다 각각 3.3배 및 4.4배 더 좋습니다.
Takeshi KUMAKI
Masakatsu ISHIZAKI
Tetsushi KOIDE
Hans Jurgen MATTAUSCH
Yasuto KURODA
Takayuki GYOHTEN
Hideyuki NODA
Katsumi DOSAKA
Kazutami ARIMOTO
Kazunori SAITO
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Takeshi KUMAKI, Masakatsu ISHIZAKI, Tetsushi KOIDE, Hans Jurgen MATTAUSCH, Yasuto KURODA, Takayuki GYOHTEN, Hideyuki NODA, Katsumi DOSAKA, Kazutami ARIMOTO, Kazunori SAITO, "Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1409-1418, September 2008, doi: 10.1093/ietele/e91-c.9.1409.
Abstract: This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm2 are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1409/_p
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@ARTICLE{e91-c_9_1409,
author={Takeshi KUMAKI, Masakatsu ISHIZAKI, Tetsushi KOIDE, Hans Jurgen MATTAUSCH, Yasuto KURODA, Takayuki GYOHTEN, Hideyuki NODA, Katsumi DOSAKA, Kazutami ARIMOTO, Kazunori SAITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor},
year={2008},
volume={E91-C},
number={9},
pages={1409-1418},
abstract={This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm2 are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.},
keywords={},
doi={10.1093/ietele/e91-c.9.1409},
ISSN={1745-1353},
month={September},}
부
TY - JOUR
TI - Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 1409
EP - 1418
AU - Takeshi KUMAKI
AU - Masakatsu ISHIZAKI
AU - Tetsushi KOIDE
AU - Hans Jurgen MATTAUSCH
AU - Yasuto KURODA
AU - Takayuki GYOHTEN
AU - Hideyuki NODA
AU - Katsumi DOSAKA
AU - Kazutami ARIMOTO
AU - Kazunori SAITO
PY - 2008
DO - 10.1093/ietele/e91-c.9.1409
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm2 are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.
ER -