The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
산술 연산을 포함한 다양한 애플리케이션을 위한 세분화된 재구성 가능한 VLSI가 개발되었습니다. Fine-grain 아키텍처에서는 로직 블록의 활용도를 높이고 스위치 블록을 줄이는 셀 기능을 정의하는 것이 중요합니다. 관점에서 비트 직렬 재구성 가능 계산에 적합한 범용 리터럴 기반 다중 값 셀이 제안됩니다. 직렬 게이팅 차동 쌍 회로는 Sum의 전가산기 회로와 범용 리터럴 회로를 구현하는 데 효과적으로 사용됩니다. 따라서 회로기술을 이용하여 간단한 논리블록을 구성할 수 있다. 더욱이, 직렬 데이터 비트의 중첩과 한 단어의 제목을 나타내는 시작 신호가 도입되는 다중 값 시그널링을 활용하여 상호 연결 복잡성을 줄일 수 있습니다. 차동쌍 회로는 전류-출력 복제에도 효과적으로 사용되어 인접한 셀에 고속 신호를 전달합니다. 평가는 90nm CMOS 설계 규칙을 기반으로 수행되었으며 제안된 셀의 면적은 다음과 같습니다. CMOS 구현에 비해 78%로 감소되었습니다. 또한 면적 시간 곱은 92%가 되고 지연 시간은 18% 증가합니다.
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Nobuaki OKADA, Michitaka KAMEYAMA, "Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1437-1443, September 2008, doi: 10.1093/ietele/e91-c.9.1437.
Abstract: A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit-serial reconfigurable computation is proposed. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a simple logic block can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple-valued signaling, where superposition of serial data bits and a start signal which indicates heading of one-word is introduced. Differential-pair circuits are also effectively employed for current-output replication, which leads to high-speed signaling to adjacent cells The evaluation is done based on 90 nm CMOS design rule, and it is made clear that the area of the proposed cell can be reduced to 78% in comparison with that of the CMOS implementatiuon. Moreover, its area-time product becomes 92% while the delay time is increased by 18%.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1437/_p
부
@ARTICLE{e91-c_9_1437,
author={Nobuaki OKADA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation},
year={2008},
volume={E91-C},
number={9},
pages={1437-1443},
abstract={A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit-serial reconfigurable computation is proposed. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a simple logic block can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple-valued signaling, where superposition of serial data bits and a start signal which indicates heading of one-word is introduced. Differential-pair circuits are also effectively employed for current-output replication, which leads to high-speed signaling to adjacent cells The evaluation is done based on 90 nm CMOS design rule, and it is made clear that the area of the proposed cell can be reduced to 78% in comparison with that of the CMOS implementatiuon. Moreover, its area-time product becomes 92% while the delay time is increased by 18%.},
keywords={},
doi={10.1093/ietele/e91-c.9.1437},
ISSN={1745-1353},
month={September},}
부
TY - JOUR
TI - Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1437
EP - 1443
AU - Nobuaki OKADA
AU - Michitaka KAMEYAMA
PY - 2008
DO - 10.1093/ietele/e91-c.9.1437
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit-serial reconfigurable computation is proposed. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a simple logic block can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple-valued signaling, where superposition of serial data bits and a start signal which indicates heading of one-word is introduced. Differential-pair circuits are also effectively employed for current-output replication, which leads to high-speed signaling to adjacent cells The evaluation is done based on 90 nm CMOS design rule, and it is made clear that the area of the proposed cell can be reduced to 78% in comparison with that of the CMOS implementatiuon. Moreover, its area-time product becomes 92% while the delay time is increased by 18%.
ER -