The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 문서에서는 3.3V 미만의 매우 낮은 공급 전압으로 매우 높은 주파수에서 작동하는 새로 개발된 FET 결합 논리(FCL) 회로에 대해 설명합니다. FCL 회로는 전류 스위치, 부하 저항기, 이미터 팔로어 및 전류를 위한 NMOS 소스 결합 트랜지스터 쌍으로 구성됩니다. 밴드갭 기준 바이어스 생성기에 의해 제어되는 소스입니다. 이 회로를 다른 고속 회로와 비교하여 특성과 성능을 논의합니다. FCL 회로에 대한 최적의 회로 매개변수도 논의되며, 스윙 전압이 클수록 회로 성능이 향상된다는 사실이 주목됩니다. 0.25μm FCL 회로의 시뮬레이션된 지연은 15V 전원 공급 장치의 경우 2.5ps 미만이며, 시뮬레이션된 최대 토글 주파수는 5V 및 10V 전원 공급 장치에서 각각 2.5GHz 및 3.3GHz를 초과합니다. 시뮬레이션 결과는 FCL 회로가 ECL 회로, NMOS 소스 결합 논리 회로를 포함하는 전류 모드 회로 중에서 가장 좋은 성능을 달성한다는 것을 보여줍니다. FCL 회로의 지연은 ECL 회로의 절반 미만입니다. FCL 회로의 최대 토글 주파수는 NMOS 소스 결합 논리 회로의 약 1.5배입니다. FCL 회로는 저가형 CMOS 기반 BiCMOS 기술을 사용하기 때문에 고가의 베이스 이미터 자체 정렬 공정과 트렌치 절연 공정이 필요한 ECL 회로보다 비용 성능이 뛰어납니다. 전류 스위치에 공핍 모드 NMOS 트랜지스터를 사용하면 FCL 회로의 최소 공급 전압을 낮출 수 있으며 이는 XNUMXV 미만입니다. FCL 회로는 멀티 Gbit/s 텔레/데이터 통신 LSI용 유망 논리 게이트 회로입니다.
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Hitoshi OKAMURA, Masaharu SATO, Satoshi NAKAMURA, Shuji KISHI, Kunio KOKUBU, "An FET Coupled Logic (FCL) Circuit for Multi-Gb/s, Low Power and Low Voltage Serial Interface BiCMOS LSIs" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 3, pp. 531-537, March 1999, doi: .
Abstract: This paper describes a newly developed FET Coupled Logic (FCL) circuit that operates at very high frequencies with very low supply voltages below 3.3 V. An FCL circuit consists of NMOS source-coupled transistor pairs for current switches, load resistors, emitter followers and current sources that are controlled by a band-gap reference bias generator. The characteristics and performance are discussed by comparing this circuit with other high-speed circuits. The optimal circuit parameters for FCL circuits are also discussed, and the fact is noted that a larger swing voltage enhances the circuit's performance. The simulated delay of a 0.25 µm FCL circuit is less than 15 ps for a 2.5 V power supply, and the simulated maximum toggle frequencies are over 5 GHz and 10 GHz at 2.5 V and 3.3 V power supply, respectively. The simulation results show that FCL circuits achieve the best performance among the current mode circuits, which include ECL circuits, NMOS source-coupled logic circuits. The delay of the FCL circuit is less than half that of an ECL circuit. The maximum toggle frequency of the FCL circuit is about triple that of NMOS source-coupled logic circuit. Because the FCL circuit uses low-cost CMOS-based BiCMOS technologies, its cost performance is superior to ECL circuits that require expensive base-emitter self-aligned processes and trench isolation processes. Using depletion-mode NMOS transistors for current switches can lower the minimum supply voltage for FCL circuits and it is below 1.5 V. The FCL circuit is a promising logic gate circuit for multi-Gbit/s tele/data communication LSIs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_3_531/_p
부
@ARTICLE{e82-c_3_531,
author={Hitoshi OKAMURA, Masaharu SATO, Satoshi NAKAMURA, Shuji KISHI, Kunio KOKUBU, },
journal={IEICE TRANSACTIONS on Electronics},
title={An FET Coupled Logic (FCL) Circuit for Multi-Gb/s, Low Power and Low Voltage Serial Interface BiCMOS LSIs},
year={1999},
volume={E82-C},
number={3},
pages={531-537},
abstract={This paper describes a newly developed FET Coupled Logic (FCL) circuit that operates at very high frequencies with very low supply voltages below 3.3 V. An FCL circuit consists of NMOS source-coupled transistor pairs for current switches, load resistors, emitter followers and current sources that are controlled by a band-gap reference bias generator. The characteristics and performance are discussed by comparing this circuit with other high-speed circuits. The optimal circuit parameters for FCL circuits are also discussed, and the fact is noted that a larger swing voltage enhances the circuit's performance. The simulated delay of a 0.25 µm FCL circuit is less than 15 ps for a 2.5 V power supply, and the simulated maximum toggle frequencies are over 5 GHz and 10 GHz at 2.5 V and 3.3 V power supply, respectively. The simulation results show that FCL circuits achieve the best performance among the current mode circuits, which include ECL circuits, NMOS source-coupled logic circuits. The delay of the FCL circuit is less than half that of an ECL circuit. The maximum toggle frequency of the FCL circuit is about triple that of NMOS source-coupled logic circuit. Because the FCL circuit uses low-cost CMOS-based BiCMOS technologies, its cost performance is superior to ECL circuits that require expensive base-emitter self-aligned processes and trench isolation processes. Using depletion-mode NMOS transistors for current switches can lower the minimum supply voltage for FCL circuits and it is below 1.5 V. The FCL circuit is a promising logic gate circuit for multi-Gbit/s tele/data communication LSIs.},
keywords={},
doi={},
ISSN={},
month={March},}
부
TY - JOUR
TI - An FET Coupled Logic (FCL) Circuit for Multi-Gb/s, Low Power and Low Voltage Serial Interface BiCMOS LSIs
T2 - IEICE TRANSACTIONS on Electronics
SP - 531
EP - 537
AU - Hitoshi OKAMURA
AU - Masaharu SATO
AU - Satoshi NAKAMURA
AU - Shuji KISHI
AU - Kunio KOKUBU
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1999
AB - This paper describes a newly developed FET Coupled Logic (FCL) circuit that operates at very high frequencies with very low supply voltages below 3.3 V. An FCL circuit consists of NMOS source-coupled transistor pairs for current switches, load resistors, emitter followers and current sources that are controlled by a band-gap reference bias generator. The characteristics and performance are discussed by comparing this circuit with other high-speed circuits. The optimal circuit parameters for FCL circuits are also discussed, and the fact is noted that a larger swing voltage enhances the circuit's performance. The simulated delay of a 0.25 µm FCL circuit is less than 15 ps for a 2.5 V power supply, and the simulated maximum toggle frequencies are over 5 GHz and 10 GHz at 2.5 V and 3.3 V power supply, respectively. The simulation results show that FCL circuits achieve the best performance among the current mode circuits, which include ECL circuits, NMOS source-coupled logic circuits. The delay of the FCL circuit is less than half that of an ECL circuit. The maximum toggle frequency of the FCL circuit is about triple that of NMOS source-coupled logic circuit. Because the FCL circuit uses low-cost CMOS-based BiCMOS technologies, its cost performance is superior to ECL circuits that require expensive base-emitter self-aligned processes and trench isolation processes. Using depletion-mode NMOS transistors for current switches can lower the minimum supply voltage for FCL circuits and it is below 1.5 V. The FCL circuit is a promising logic gate circuit for multi-Gbit/s tele/data communication LSIs.
ER -