The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
VLSI 제조 테스트 시스템의 이산 이벤트 시뮬레이션과 세부 매개변수 모델을 결합한 시뮬레이션 방법은 시뮬레이션 결과를 일본 반도체 회사의 원칩 마이크로컴퓨터의 실제 웨이퍼 테스트 시설의 실제 결과와 비교하여 검증됩니다. 시뮬레이션 결과는 실제 결과와 거의 일치하는 것으로 나타났습니다. 검증된 시뮬레이션 방법을 적용하여 여러 칩을 동시에 테스트할 수 있는 LSI 테스터의 웨이퍼 테스트 공정에 도입할 때의 경제적 효과를 평가합니다. 칩당 테스트 비용과 평균 테스트 TAT를 모두 고려하면 LSI 테스터가 동시에 테스트하는 최적의 칩 수는 4개인 것으로 나타났습니다.
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Akihisa CHIKAMURA, Koji NAKAMAE, Hiromu FUJIOKA, "Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 6, pp. 1013-1017, June 1999, doi: .
Abstract: Our simulation method by using a combination of discrete event simulation and detailed parametric models of the VLSI manufacturing test system is verified by comparing simulated results with actual ones of a real wafer test facility of one-chip microcomputer in a Japanese semiconductor company. The simulated results are found to be in close agreement with the actual ones. As an application of the verified simulation method, we evaluate the economic effect of the introduction in the wafer test process of LSI testers that allows us to test multiple chips simultaneously. It is found that the optimum number of chips simultaneously tested by an LSI tester is 4 when considering both of the test cost per chip and the average test TAT.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_6_1013/_p
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@ARTICLE{e82-c_6_1013,
author={Akihisa CHIKAMURA, Koji NAKAMAE, Hiromu FUJIOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application},
year={1999},
volume={E82-C},
number={6},
pages={1013-1017},
abstract={Our simulation method by using a combination of discrete event simulation and detailed parametric models of the VLSI manufacturing test system is verified by comparing simulated results with actual ones of a real wafer test facility of one-chip microcomputer in a Japanese semiconductor company. The simulated results are found to be in close agreement with the actual ones. As an application of the verified simulation method, we evaluate the economic effect of the introduction in the wafer test process of LSI testers that allows us to test multiple chips simultaneously. It is found that the optimum number of chips simultaneously tested by an LSI tester is 4 when considering both of the test cost per chip and the average test TAT.},
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application
T2 - IEICE TRANSACTIONS on Electronics
SP - 1013
EP - 1017
AU - Akihisa CHIKAMURA
AU - Koji NAKAMAE
AU - Hiromu FUJIOKA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1999
AB - Our simulation method by using a combination of discrete event simulation and detailed parametric models of the VLSI manufacturing test system is verified by comparing simulated results with actual ones of a real wafer test facility of one-chip microcomputer in a Japanese semiconductor company. The simulated results are found to be in close agreement with the actual ones. As an application of the verified simulation method, we evaluate the economic effect of the introduction in the wafer test process of LSI testers that allows us to test multiple chips simultaneously. It is found that the optimum number of chips simultaneously tested by an LSI tester is 4 when considering both of the test cost per chip and the average test TAT.
ER -