The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 기존 엔지니어링 워크스테이션에서 적당한 속도로 실행되도록 설계된 엄격한 벡터 3D 리소그래피 시뮬레이터 METROPOLE-3D를 제시합니다. METROPOLE-3D는 Maxwell의 방정식을 3차원에서 엄격하게 풀어 비수직 입사광이 비평면 구조에서 산란되고 전송되는 방식을 모델링합니다. METROPOLE-3D는 포토마스크 시뮬레이터, 노출 시뮬레이터, 노출 후 베이킹 모듈, 3D 개발 모듈 등 여러 시뮬레이션 모듈로 구성됩니다. 이 시뮬레이터는 반사 노칭 문제 및 반사 방지 코팅(ARC) 레이어 최적화를 포함한 레이아웃 인쇄 가능성/제조 가능성 분석과 같은 최첨단 VLSI 제조 공정에서 직면하는 광범위한 프레싱 엔지니어링 문제에 적용되었습니다. 마지막으로 엄격한 시뮬레이터를 사용하여 XNUMXD 오염-결함 변환 연구가 성공적으로 수행되었습니다.
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부
Andrzej J. STROJWAS, Xiaolei LI, Kevin D. LUCAS, "METROPOLE-3D: An Efficient and Rigorous 3D Photolithography Simulator" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 6, pp. 821-829, June 1999, doi: .
Abstract: In this paper we present a rigorous vector 3D lithography simulator METROPOLE-3D which is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwell's equations rigorously in three dimensions to model how the non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE-3D consists of several simulation modules: photomask simulator, exposure simulator, post-exposure baking module and 3D development module. This simulator has been applied to a wide range of pressing engineering problems encountered in state-of-the-art VLSI fabrication processes, such as layout printability/manufacturability analysis including reflective notching problems and optimization of an anti-reflective coating (ARC) layer. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_6_821/_p
부
@ARTICLE{e82-c_6_821,
author={Andrzej J. STROJWAS, Xiaolei LI, Kevin D. LUCAS, },
journal={IEICE TRANSACTIONS on Electronics},
title={METROPOLE-3D: An Efficient and Rigorous 3D Photolithography Simulator},
year={1999},
volume={E82-C},
number={6},
pages={821-829},
abstract={In this paper we present a rigorous vector 3D lithography simulator METROPOLE-3D which is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwell's equations rigorously in three dimensions to model how the non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE-3D consists of several simulation modules: photomask simulator, exposure simulator, post-exposure baking module and 3D development module. This simulator has been applied to a wide range of pressing engineering problems encountered in state-of-the-art VLSI fabrication processes, such as layout printability/manufacturability analysis including reflective notching problems and optimization of an anti-reflective coating (ARC) layer. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.},
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - METROPOLE-3D: An Efficient and Rigorous 3D Photolithography Simulator
T2 - IEICE TRANSACTIONS on Electronics
SP - 821
EP - 829
AU - Andrzej J. STROJWAS
AU - Xiaolei LI
AU - Kevin D. LUCAS
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1999
AB - In this paper we present a rigorous vector 3D lithography simulator METROPOLE-3D which is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwell's equations rigorously in three dimensions to model how the non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE-3D consists of several simulation modules: photomask simulator, exposure simulator, post-exposure baking module and 3D development module. This simulator has been applied to a wide range of pressing engineering problems encountered in state-of-the-art VLSI fabrication processes, such as layout printability/manufacturability analysis including reflective notching problems and optimization of an anti-reflective coating (ARC) layer. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.
ER -