The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 실제 초대형 집적 장치(ULSI)에 대해 나노미터 수준의 정밀도와 전기적 특성과의 좋은 상관성을 갖는 CD-SEM의 새로운 측정 방법을 설명합니다. 형상 크기가 감소함에 따라 측정할 패턴이 곡선 모양으로 변하는 경향이 있습니다. 이러한 패턴을 5 nm 정도의 측정 정밀도 내에서 측정하려면 64차원 측정이 효과적입니다. 여기에서는 임계 치수가 측정 패턴의 영역 값에서 파생되는 새로운 측정 알고리즘을 보고합니다. 이 측정 방법을 3.6-Mbit DRAM의 실제 장치에 적용하여 게이트 선폭 측정의 경우 5.6 nm, 홀 직경 측정의 경우 XNUMX nm의 재현성을 확인했습니다. 또한, 게이트 선폭의 측정값은 문턱전압과 강한 상관관계를 가지며, 홀 직경의 측정값도 접촉저항과 강한 상관관계를 갖는 것을 확인하였다.
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Fumio KOMATSU, Motosuke MIYOSHI, Hiromu FUJIOKA, "A New CD Measurement Method Linked with the Electrical Properties of Devices" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 7, pp. 1347-1352, July 1999, doi: .
Abstract: This paper describes a new measurement method of a CD-SEM with nanometer-level precision and good correlation with electrical characteristics for an actual device of ultra-large-scale integration (ULSI). With the decrease in feature size, the pattern to be measured tends to become a curved shape. In order to measure such a pattern within measurement precision on the order of 5 nm, two-dimensional measurement is effective. Here we report a new measurement algorithm featuring that the critical dimension is derived from the value of the area of a measurement pattern. We apply this measurement method to actual device of 64-Mbit DRAM and confirm the reproducibility of 3.6 nm for the gate linewidth measurement, and that of 5.6 nm for the hole diameter measurement. Furthermore, we verify that the measurement values of the gate linewidth have a strong correlation with the threshold voltage and those of the hole diameter also have a strong correlation with the contact resistance, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_7_1347/_p
부
@ARTICLE{e82-c_7_1347,
author={Fumio KOMATSU, Motosuke MIYOSHI, Hiromu FUJIOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A New CD Measurement Method Linked with the Electrical Properties of Devices},
year={1999},
volume={E82-C},
number={7},
pages={1347-1352},
abstract={This paper describes a new measurement method of a CD-SEM with nanometer-level precision and good correlation with electrical characteristics for an actual device of ultra-large-scale integration (ULSI). With the decrease in feature size, the pattern to be measured tends to become a curved shape. In order to measure such a pattern within measurement precision on the order of 5 nm, two-dimensional measurement is effective. Here we report a new measurement algorithm featuring that the critical dimension is derived from the value of the area of a measurement pattern. We apply this measurement method to actual device of 64-Mbit DRAM and confirm the reproducibility of 3.6 nm for the gate linewidth measurement, and that of 5.6 nm for the hole diameter measurement. Furthermore, we verify that the measurement values of the gate linewidth have a strong correlation with the threshold voltage and those of the hole diameter also have a strong correlation with the contact resistance, respectively.},
keywords={},
doi={},
ISSN={},
month={July},}
부
TY - JOUR
TI - A New CD Measurement Method Linked with the Electrical Properties of Devices
T2 - IEICE TRANSACTIONS on Electronics
SP - 1347
EP - 1352
AU - Fumio KOMATSU
AU - Motosuke MIYOSHI
AU - Hiromu FUJIOKA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1999
AB - This paper describes a new measurement method of a CD-SEM with nanometer-level precision and good correlation with electrical characteristics for an actual device of ultra-large-scale integration (ULSI). With the decrease in feature size, the pattern to be measured tends to become a curved shape. In order to measure such a pattern within measurement precision on the order of 5 nm, two-dimensional measurement is effective. Here we report a new measurement algorithm featuring that the critical dimension is derived from the value of the area of a measurement pattern. We apply this measurement method to actual device of 64-Mbit DRAM and confirm the reproducibility of 3.6 nm for the gate linewidth measurement, and that of 5.6 nm for the hole diameter measurement. Furthermore, we verify that the measurement values of the gate linewidth have a strong correlation with the threshold voltage and those of the hole diameter also have a strong correlation with the contact resistance, respectively.
ER -