The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
전자 전하의 불연속성을 활용하는 단일 전자 터널링(SET) 회로를 사용하는 다중 값 논리 인버터가 제안되었습니다. 2개의 SET 트랜지스터만으로 구성된 인버터 회로는 메모리 기능과 다치 논리를 위한 인버터 기능을 갖추고 있습니다. 두 개의 인버터를 결합함으로써 다치 논리를 위한 양자화 회로와 D 플립플롭 회로를 콤팩트하게 구성할 수 있습니다. 임계값 장치는 인버터 회로에 두 개 이상의 입력 커패시터를 연결하여 컴팩트하게 구성할 수 있습니다. 4차 전가산기 회로는 두 개의 임계값 장치를 사용하여 구성할 수 있습니다. 구현 문제도 논의됩니다.
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Masamichi AKAZAWA, Kentarou KANAAMI, Takashi YAMADA, Yoshihito AMEMIYA, "Multiple-Valued Inverter Using a Single-Electron-Tunneling Circuit" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 9, pp. 1607-1614, September 1999, doi: .
Abstract: A multiple-valued logic inverter is proposed that uses single-electron-tunneling (SET) circuits in which the discreteness of the electron charge is utilized. The inverter circuit, which is composed of only two SET transistors, has a memory function as well as an inverter function for multiple-valued logic. A quantizing circuit and a D flip-flop circuit for multiple-valued logic can be compactly constructed by combining two inverters. A threshold device can be compactly constructed by attaching more than one input capacitor to the inverter circuit. A quaternary full adder circuit can be constructed by using two threshold devices. Implementation issues are also discussed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_9_1607/_p
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@ARTICLE{e82-c_9_1607,
author={Masamichi AKAZAWA, Kentarou KANAAMI, Takashi YAMADA, Yoshihito AMEMIYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Multiple-Valued Inverter Using a Single-Electron-Tunneling Circuit},
year={1999},
volume={E82-C},
number={9},
pages={1607-1614},
abstract={A multiple-valued logic inverter is proposed that uses single-electron-tunneling (SET) circuits in which the discreteness of the electron charge is utilized. The inverter circuit, which is composed of only two SET transistors, has a memory function as well as an inverter function for multiple-valued logic. A quantizing circuit and a D flip-flop circuit for multiple-valued logic can be compactly constructed by combining two inverters. A threshold device can be compactly constructed by attaching more than one input capacitor to the inverter circuit. A quaternary full adder circuit can be constructed by using two threshold devices. Implementation issues are also discussed.},
keywords={},
doi={},
ISSN={},
month={September},}
부
TY - JOUR
TI - Multiple-Valued Inverter Using a Single-Electron-Tunneling Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 1607
EP - 1614
AU - Masamichi AKAZAWA
AU - Kentarou KANAAMI
AU - Takashi YAMADA
AU - Yoshihito AMEMIYA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1999
AB - A multiple-valued logic inverter is proposed that uses single-electron-tunneling (SET) circuits in which the discreteness of the electron charge is utilized. The inverter circuit, which is composed of only two SET transistors, has a memory function as well as an inverter function for multiple-valued logic. A quantizing circuit and a D flip-flop circuit for multiple-valued logic can be compactly constructed by combining two inverters. A threshold device can be compactly constructed by attaching more than one input capacitor to the inverter circuit. A quaternary full adder circuit can be constructed by using two threshold devices. Implementation issues are also discussed.
ER -