The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
딥 서브미크론 설계에서 저전력 소모를 달성하기 위한 NMOS 4상 동적 로직 방식을 설명합니다. 이러한 방식에서는 단락 전류가 제거되고, 또한 천이 신호의 전압 스윙이 감소되어 전력 감소가 효과적으로 향상됩니다. 첫째, 정적 CMOS 로직 및 동적 도미노 CMOS 로직과 비교하여 이 4상 동적 로직의 특징을 지정합니다. 그런 다음 다수의 로직 모듈을 사용하여 4상 동적 로직, 정적 CMOS 로직, 동적 CMOS 로직 및 패스 트랜지스터 로직에 대한 전력 시뮬레이션을 시도하여 NMOS 4상 동적 로직이 가장 강력한 전력임을 보여줍니다. -효율적인. 또한, 게이트 지연 시뮬레이션을 통해 로직 블록에 얼마나 많은 트랜지스터를 넣을 수 있는지에 대해서도 논의합니다.
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부
Bao-Yu SONG, Makoto FURUIE, Yukihiro YOSHIDA, Takao ONOYE, Isao SHIRAKAWA, "Low-Power Scheme of NMOS 4-Phase Dynamic Logic" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 9, pp. 1772-1776, September 1999, doi: .
Abstract: An NMOS 4-phase dynamic logic scheme is described, which is intended to achieve low-power consumption in the deep submicron design. In this scheme, the short-circuit current is eliminated, and moreover, the voltage swing of transition signals is reduced, resulting in enhancing power reduction effectively. First, distinctive features of this 4-phase dynamic logic are specified, as compared with the static CMOS logic and dynamic domino CMOS logic. Then, power simulations are attempted for the 4-phase dynamic logic, static CMOS logic, dynamic CMOS logic, and pass-transistor logic, by using a number of logic modules, which demonstrate that the NMOS 4-phase dynamic logic is the most power-efficient. Moreover, through the gate delay simulation, the capability of how many transistors can be packed in a logic block is also discussed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_9_1772/_p
부
@ARTICLE{e82-c_9_1772,
author={Bao-Yu SONG, Makoto FURUIE, Yukihiro YOSHIDA, Takao ONOYE, Isao SHIRAKAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Power Scheme of NMOS 4-Phase Dynamic Logic},
year={1999},
volume={E82-C},
number={9},
pages={1772-1776},
abstract={An NMOS 4-phase dynamic logic scheme is described, which is intended to achieve low-power consumption in the deep submicron design. In this scheme, the short-circuit current is eliminated, and moreover, the voltage swing of transition signals is reduced, resulting in enhancing power reduction effectively. First, distinctive features of this 4-phase dynamic logic are specified, as compared with the static CMOS logic and dynamic domino CMOS logic. Then, power simulations are attempted for the 4-phase dynamic logic, static CMOS logic, dynamic CMOS logic, and pass-transistor logic, by using a number of logic modules, which demonstrate that the NMOS 4-phase dynamic logic is the most power-efficient. Moreover, through the gate delay simulation, the capability of how many transistors can be packed in a logic block is also discussed.},
keywords={},
doi={},
ISSN={},
month={September},}
부
TY - JOUR
TI - Low-Power Scheme of NMOS 4-Phase Dynamic Logic
T2 - IEICE TRANSACTIONS on Electronics
SP - 1772
EP - 1776
AU - Bao-Yu SONG
AU - Makoto FURUIE
AU - Yukihiro YOSHIDA
AU - Takao ONOYE
AU - Isao SHIRAKAWA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1999
AB - An NMOS 4-phase dynamic logic scheme is described, which is intended to achieve low-power consumption in the deep submicron design. In this scheme, the short-circuit current is eliminated, and moreover, the voltage swing of transition signals is reduced, resulting in enhancing power reduction effectively. First, distinctive features of this 4-phase dynamic logic are specified, as compared with the static CMOS logic and dynamic domino CMOS logic. Then, power simulations are attempted for the 4-phase dynamic logic, static CMOS logic, dynamic CMOS logic, and pass-transistor logic, by using a number of logic modules, which demonstrate that the NMOS 4-phase dynamic logic is the most power-efficient. Moreover, through the gate delay simulation, the capability of how many transistors can be packed in a logic block is also discussed.
ER -