The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
무작위 변조는 셀별로 MOSFET 임계 전압이 변경되는 것을 의미합니다. 본 논문에서는 이 기술이 대기 모드는 물론 활성 모드와 절전 모드에서도 임계값 이하의 누설 전류를 줄이기 때문에 Sub-2V CMOS 설계에 필수적이라고 주장합니다. 우리는 낮은 V의 비율을 점진적으로 변화시키는 점진적 변조 방식을 발견했습니다.th 경로 지연에 따른 셀이 최선의 접근 방식입니다. 최소 누설 전류를 달성하기 위해 최적의 임계 전압 쌍을 결정하는 방법도 설명합니다. 마이크로프로세서에 대한 실험 결과에 따르면 점진적 변조는 회로 성능을 저하시키지 않으면서 기존의 단일 낮은 임계값 전압 설계에 비해 임계값 미만 누설 전류를 75% ~ 90% 감소시키는 것으로 나타났습니다.
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Naoki KATO, Yohei AKITA, Mitsuru HIRAKI, Takeo YAMASHITA, Teruhisa SHIMIZU, Fuyuhiko MAKI, Kazuo YANO, "Random Modulation: Multi-Threshold-Voltage Design Methodology in Sub-2-V Power Supply CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 11, pp. 1747-1754, November 2000, doi: .
Abstract: Random modulation refers to the changing of the MOSFET threshold voltage cell by cell. This paper claims it is essential in sub-2-V CMOS design because it reduces the sub-threshold leakage current even in the active and sleep modes as well as in the stand-by mode. We found that a gradated modulation scheme, which gradually changes the ratio of low- Vth cells according to the path-delay, is the best approach. To achieve the minimal leakage current, the way of determining the optimum pair of threshold voltages is also described. Experimental results for microprocessor show that gradated modulation reduces sub-threshold leakage current by 75% to 90% compared to conventional single-low-threshold voltage design without degrading the performance of the circuits.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_11_1747/_p
부
@ARTICLE{e83-c_11_1747,
author={Naoki KATO, Yohei AKITA, Mitsuru HIRAKI, Takeo YAMASHITA, Teruhisa SHIMIZU, Fuyuhiko MAKI, Kazuo YANO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Random Modulation: Multi-Threshold-Voltage Design Methodology in Sub-2-V Power Supply CMOS},
year={2000},
volume={E83-C},
number={11},
pages={1747-1754},
abstract={Random modulation refers to the changing of the MOSFET threshold voltage cell by cell. This paper claims it is essential in sub-2-V CMOS design because it reduces the sub-threshold leakage current even in the active and sleep modes as well as in the stand-by mode. We found that a gradated modulation scheme, which gradually changes the ratio of low- Vth cells according to the path-delay, is the best approach. To achieve the minimal leakage current, the way of determining the optimum pair of threshold voltages is also described. Experimental results for microprocessor show that gradated modulation reduces sub-threshold leakage current by 75% to 90% compared to conventional single-low-threshold voltage design without degrading the performance of the circuits.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - Random Modulation: Multi-Threshold-Voltage Design Methodology in Sub-2-V Power Supply CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 1747
EP - 1754
AU - Naoki KATO
AU - Yohei AKITA
AU - Mitsuru HIRAKI
AU - Takeo YAMASHITA
AU - Teruhisa SHIMIZU
AU - Fuyuhiko MAKI
AU - Kazuo YANO
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2000
AB - Random modulation refers to the changing of the MOSFET threshold voltage cell by cell. This paper claims it is essential in sub-2-V CMOS design because it reduces the sub-threshold leakage current even in the active and sleep modes as well as in the stand-by mode. We found that a gradated modulation scheme, which gradually changes the ratio of low- Vth cells according to the path-delay, is the best approach. To achieve the minimal leakage current, the way of determining the optimum pair of threshold voltages is also described. Experimental results for microprocessor show that gradated modulation reduces sub-threshold leakage current by 75% to 90% compared to conventional single-low-threshold voltage design without degrading the performance of the circuits.
ER -