The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
고온 초전도체 조셉슨 접합 기술의 최근 진행 상황을 향후 디지털 회로에 적용할 관점에서 검토합니다. 지금까지 개발된 다양한 유형의 조셉슨 접합 중에서 금속-절연체 전이 부근에 산화물 재료로 구성된 장벽층을 갖춘 램프 에지형 접합은 다음과 같은 장점으로 인해 디지털 회로 응용에 대한 모든 요구 사항을 충족할 수 있는 독특한 기회를 제공하는 것으로 보입니다. 작은 접합 치수, 과도한 감쇠 특성 및 상대적으로 높은 IcRn 약 30-40K의 온도에서 제품 값. 최근 개발된 인터페이스 엔지니어링 접합은 이러한 유형의 접합으로 분류될 수 있습니다. 이러한 접합은 또한 장벽의 국지적 상태를 통한 쿠퍼 쌍의 공진 터널링 가능성과 관련하여 물리학에서 흥미로운 문제를 제기합니다. 실제 적용의 관점에서 볼 때, 접합 매개변수의 확산을 개선하는 것은 현재 제조 기술에 있어 여전히 심각한 과제입니다. 현재 이와 관련하여 인터페이스 엔지니어링 접합이 가장 유망한 것으로 보이지만 현재 제조 기술에서 약 1%의 8σ 확산은 대규모 집적 회로 제조에 만족스럽지 않습니다. 인터페이스 엔지니어링 접합의 장벽 형성 메커니즘에 대한 자세한 이해는 이 특정 제조 기술을 발전시킬 뿐만 아니라 램프 에지 구조를 활용하는 다른 접합 기술을 개선하는 데에도 필수적입니다.
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부
Jiro YOSHIDA, "Recent Progress of High-Temperature Superconductor Josephson Junction Technology for Digital Circuit Applications" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 1, pp. 49-59, January 2000, doi: .
Abstract: Recent progress of high-temperature superconductor Josephson junction technology is reviewed in the light of the future application to digital circuits. Among various types of Josephson junctions so far developed, ramp-edge-type junctions with a barrier layer composed of oxide materials in the vicinity of metal-insulator transition seem to offer a unique opportunity to fulfill all the requirements for digital circuit applications by virtue of their small junction dimensions, overdamped properties and relatively high IcRn product values at the temperature of around 30-40 K. Recently developed interface engineered junctions can be classified as junctions of this type. These junctions also raise an interesting problem in physics concerning the possibility of resonant tunneling of Cooper pairs via localized states in the barrier. From the viewpoint of practical applications, the improvement of the spread of the junction parameters is still a serious challenge to the present fabrication technology. Although interface engineered junctions seem to be most promising in this regard at present, 1σ spread of around 8% in the present fabrication technology is far from satisfactory for the fabrication of large-scale integrated circuits. The detailed understanding of the barrier formation mechanism in the interface engineered junction is indispensable not only for advancing this particular fabrication technology but also for improving other junction technology utilizing ramp-edge structures.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_1_49/_p
부
@ARTICLE{e83-c_1_49,
author={Jiro YOSHIDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Recent Progress of High-Temperature Superconductor Josephson Junction Technology for Digital Circuit Applications},
year={2000},
volume={E83-C},
number={1},
pages={49-59},
abstract={Recent progress of high-temperature superconductor Josephson junction technology is reviewed in the light of the future application to digital circuits. Among various types of Josephson junctions so far developed, ramp-edge-type junctions with a barrier layer composed of oxide materials in the vicinity of metal-insulator transition seem to offer a unique opportunity to fulfill all the requirements for digital circuit applications by virtue of their small junction dimensions, overdamped properties and relatively high IcRn product values at the temperature of around 30-40 K. Recently developed interface engineered junctions can be classified as junctions of this type. These junctions also raise an interesting problem in physics concerning the possibility of resonant tunneling of Cooper pairs via localized states in the barrier. From the viewpoint of practical applications, the improvement of the spread of the junction parameters is still a serious challenge to the present fabrication technology. Although interface engineered junctions seem to be most promising in this regard at present, 1σ spread of around 8% in the present fabrication technology is far from satisfactory for the fabrication of large-scale integrated circuits. The detailed understanding of the barrier formation mechanism in the interface engineered junction is indispensable not only for advancing this particular fabrication technology but also for improving other junction technology utilizing ramp-edge structures.},
keywords={},
doi={},
ISSN={},
month={January},}
부
TY - JOUR
TI - Recent Progress of High-Temperature Superconductor Josephson Junction Technology for Digital Circuit Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 49
EP - 59
AU - Jiro YOSHIDA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2000
AB - Recent progress of high-temperature superconductor Josephson junction technology is reviewed in the light of the future application to digital circuits. Among various types of Josephson junctions so far developed, ramp-edge-type junctions with a barrier layer composed of oxide materials in the vicinity of metal-insulator transition seem to offer a unique opportunity to fulfill all the requirements for digital circuit applications by virtue of their small junction dimensions, overdamped properties and relatively high IcRn product values at the temperature of around 30-40 K. Recently developed interface engineered junctions can be classified as junctions of this type. These junctions also raise an interesting problem in physics concerning the possibility of resonant tunneling of Cooper pairs via localized states in the barrier. From the viewpoint of practical applications, the improvement of the spread of the junction parameters is still a serious challenge to the present fabrication technology. Although interface engineered junctions seem to be most promising in this regard at present, 1σ spread of around 8% in the present fabrication technology is far from satisfactory for the fabrication of large-scale integrated circuits. The detailed understanding of the barrier formation mechanism in the interface engineered junction is indispensable not only for advancing this particular fabrication technology but also for improving other junction technology utilizing ramp-edge structures.
ER -