The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 문서에서는 단일 칩 MPEG-2 비디오 인코더의 아키텍처를 제시하고 그 유연성과 유용성을 보여줍니다. 0.25계층 협력을 기반으로 하는 아키텍처는 다양성, 확장성 및 비디오 품질의 관점에서 인코더를 향상시키는 유연한 데이터 전송을 제공합니다. LSI는 XNUMXμm XNUMX금속 CMOS 공정으로 성공적으로 제작되었습니다. 작은 크기와 낮은 전력 소비로 인해 DVD 레코더, PC 카드 인코더 및 HDTV 인코더와 같은 광범위한 애플리케이션에 이상적입니다.
Mitsuo IKEDA
Toshio KONDO
Koyo NITTA
Kazuhito SUGURI
Takeshi YOSHITOME
Toshihiro MINAMI
Jiro NAGANUMA
Takeshi OGURA
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
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Mitsuo IKEDA, Toshio KONDO, Koyo NITTA, Kazuhito SUGURI, Takeshi YOSHITOME, Toshihiro MINAMI, Jiro NAGANUMA, Takeshi OGURA, "Three-Layer Cooperative Architecture for MPEG-2 Video Encoder LSI" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 2, pp. 170-178, February 2000, doi: .
Abstract: This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-µm four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_2_170/_p
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@ARTICLE{e83-c_2_170,
author={Mitsuo IKEDA, Toshio KONDO, Koyo NITTA, Kazuhito SUGURI, Takeshi YOSHITOME, Toshihiro MINAMI, Jiro NAGANUMA, Takeshi OGURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Three-Layer Cooperative Architecture for MPEG-2 Video Encoder LSI},
year={2000},
volume={E83-C},
number={2},
pages={170-178},
abstract={This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-µm four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.},
keywords={},
doi={},
ISSN={},
month={February},}
부
TY - JOUR
TI - Three-Layer Cooperative Architecture for MPEG-2 Video Encoder LSI
T2 - IEICE TRANSACTIONS on Electronics
SP - 170
EP - 178
AU - Mitsuo IKEDA
AU - Toshio KONDO
AU - Koyo NITTA
AU - Kazuhito SUGURI
AU - Takeshi YOSHITOME
AU - Toshihiro MINAMI
AU - Jiro NAGANUMA
AU - Takeshi OGURA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2000
AB - This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-µm four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.
ER -