The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 집합 연관 캐시에 대해 높은 성능과 낮은 에너지 소비를 달성하기 위한 새로운 접근 방식을 제안합니다. 캐시라고 합니다. 길 예측 집합 연관 캐시, 정상적인 캐시 액세스를 시작하기 전에 메모리 주소로 지정된 집합에서 프로세서가 원하는 데이터를 포함할 가능성이 있는 단일 방법을 추론적으로 선택합니다. 세트의 모든 경로에 액세스하는 대신 예측된 단일 경로에만 액세스함으로써 에너지 소비를 줄일 수 있습니다. 길 예측 캐시가 잘 수행되기 위해서는 길 예측의 정확성이 중요합니다. 본 논문에서는 대부분의 벤치마크 프로그램에서 MRU(가장 최근에 사용됨) 기반 방식 예측의 정확도가 90% 이상임을 보여줍니다. 제안된 방향 예측 캐시는 기존의 집합 연관 캐시에 비해 ED(energy-delay) 곱을 60~70% 향상시킵니다.
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부
Koji INOUE, Tohru ISHIHARA, Kazuaki MURAKAMI, "A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 2, pp. 186-194, February 2000, doi: .
Abstract: This paper proposes a new approach to achieving high performance and low energy consumption for set-associative caches. The cache, called way-predicting set-associative cache, speculatively selects a single way, which is likely to contain the data desired by the processor, from the set designated by a memory address, before it starts a normal cache access. By accessing only the single way predicted, instead of accessing all the ways in a set, energy consumption can be reduced. In order for the way-predicting cache to perform well, accuracy of way prediction is important. This paper shows that the accuracy of an MRU (most recently used)-based way prediction is higher than 90% for most of the benchmark programs. The proposed way-predicting cache improves the ED (energy-delay) product by 60-70% compared to the conventional set-associative cache.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_2_186/_p
부
@ARTICLE{e83-c_2_186,
author={Koji INOUE, Tohru ISHIHARA, Kazuaki MURAKAMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection},
year={2000},
volume={E83-C},
number={2},
pages={186-194},
abstract={This paper proposes a new approach to achieving high performance and low energy consumption for set-associative caches. The cache, called way-predicting set-associative cache, speculatively selects a single way, which is likely to contain the data desired by the processor, from the set designated by a memory address, before it starts a normal cache access. By accessing only the single way predicted, instead of accessing all the ways in a set, energy consumption can be reduced. In order for the way-predicting cache to perform well, accuracy of way prediction is important. This paper shows that the accuracy of an MRU (most recently used)-based way prediction is higher than 90% for most of the benchmark programs. The proposed way-predicting cache improves the ED (energy-delay) product by 60-70% compared to the conventional set-associative cache.},
keywords={},
doi={},
ISSN={},
month={February},}
부
TY - JOUR
TI - A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection
T2 - IEICE TRANSACTIONS on Electronics
SP - 186
EP - 194
AU - Koji INOUE
AU - Tohru ISHIHARA
AU - Kazuaki MURAKAMI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2000
AB - This paper proposes a new approach to achieving high performance and low energy consumption for set-associative caches. The cache, called way-predicting set-associative cache, speculatively selects a single way, which is likely to contain the data desired by the processor, from the set designated by a memory address, before it starts a normal cache access. By accessing only the single way predicted, instead of accessing all the ways in a set, energy consumption can be reduced. In order for the way-predicting cache to perform well, accuracy of way prediction is important. This paper shows that the accuracy of an MRU (most recently used)-based way prediction is higher than 90% for most of the benchmark programs. The proposed way-predicting cache improves the ED (energy-delay) product by 60-70% compared to the conventional set-associative cache.
ER -