The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이전에도 임베디드 DRAM 기술을 활용한 다양한 종류의 고대역폭 아키텍처가 제시되었습니다. 대부분의 경우 넓은 버스 구현 및/또는 빠른 버스 속도를 사용하는데, 이는 다이 면적의 불이익과 동시에 많은 전력 소비를 초래합니다. 제안된 단일 종단 읽기-수정-쓰기 버스는 동일한 버스 크기와 동일한 버스 속도를 유지하면서 대역폭을 두 배로 늘립니다. 데이터 버스는 각각 동시에 작동하는 1k 비트 읽기 버스와 1k 비트 쓰기 버스로 구성되며 진폭은 0V ~ 1V이므로 측정된 전력 소비는 0.3MHz 주파수에서 166W에 불과합니다. . 프로그래밍 가능한 페이지 크기는 페이지 누락률을 줄이고 넓은 버스 및 빠른 속도 접근 방식에 필적하는 대역폭을 효율적으로 향상시킵니다. 제안된 모든 기능은 3D 프레임 버퍼에 구현되어 42.4G-BPS 대역폭을 달성합니다.
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부
Kazunari INOUE, Hideaki ABE, Kaori MORI, Shuji FUKAGAWA, "A Low-Voltage 42.4 G-BPS Single-Ended Read-Modify-Write Bus and Programmable Page-Size on a 3D Frame-Buffer" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 2, pp. 195-204, February 2000, doi: .
Abstract: Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and/or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing single-ended read-modify-write bus increases the bandwidth twice as high, while it maintains the same bus size and the same bus speed. The data-bus comprises 1 k-bit read-bus and 1 k-bit write-bus that each works concurrently, and has amplitude from 0 V to 1 V, hence the measured power consumption is only 0.3 W at a frequency of 166 MHz. A programmable page-size reduces the page miss-rate and efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D frame-buffer to achieve 42.4 G-BPS bandwidth.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_2_195/_p
부
@ARTICLE{e83-c_2_195,
author={Kazunari INOUE, Hideaki ABE, Kaori MORI, Shuji FUKAGAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Voltage 42.4 G-BPS Single-Ended Read-Modify-Write Bus and Programmable Page-Size on a 3D Frame-Buffer},
year={2000},
volume={E83-C},
number={2},
pages={195-204},
abstract={Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and/or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing single-ended read-modify-write bus increases the bandwidth twice as high, while it maintains the same bus size and the same bus speed. The data-bus comprises 1 k-bit read-bus and 1 k-bit write-bus that each works concurrently, and has amplitude from 0 V to 1 V, hence the measured power consumption is only 0.3 W at a frequency of 166 MHz. A programmable page-size reduces the page miss-rate and efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D frame-buffer to achieve 42.4 G-BPS bandwidth.},
keywords={},
doi={},
ISSN={},
month={February},}
부
TY - JOUR
TI - A Low-Voltage 42.4 G-BPS Single-Ended Read-Modify-Write Bus and Programmable Page-Size on a 3D Frame-Buffer
T2 - IEICE TRANSACTIONS on Electronics
SP - 195
EP - 204
AU - Kazunari INOUE
AU - Hideaki ABE
AU - Kaori MORI
AU - Shuji FUKAGAWA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2000
AB - Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and/or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing single-ended read-modify-write bus increases the bandwidth twice as high, while it maintains the same bus size and the same bus speed. The data-bus comprises 1 k-bit read-bus and 1 k-bit write-bus that each works concurrently, and has amplitude from 0 V to 1 V, hence the measured power consumption is only 0.3 W at a frequency of 166 MHz. A programmable page-size reduces the page miss-rate and efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D frame-buffer to achieve 42.4 G-BPS bandwidth.
ER -