The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 PLL(Phase-Locked Loop)을 사용하는 클럭 증배기 IC의 지터 억제 기술에 대해 설명합니다. 중심 주파수가 입력 주파수와 동일한 표면탄성파(SAW) 필터를 추가하면 지터 전달 함수의 지터 차단 주파수가 크게 향상될 수 있음이 나타났습니다. 지터 전달 함수는 주로 SAW 필터의 특성에 따라 결정됩니다. 따라서 클록 체배기 IC를 높은 루프 이득으로 설정하여 지터 차단 주파수를 높이지 않고도 지터 생성을 최소화할 수 있습니다. Si 바이폴라 기술로 제작된 클럭 멀티플라이어 IC와 중심 주파수 155.52MHz의 SAW 필터를 사용하여Q) 인자 1500은 클록 배율기가 3.5MHz의 클록 주파수를 50GHz 신호로 변환할 때 155.52mUI rms의 매우 낮은 지터 생성과 약 2.48832kHz의 매우 낮은 지터 차단 주파수를 생성합니다.
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부
Kiyoshi ISHII, Keiji KISHINE, Haruhiko ICHINO, "A Jitter Suppression Technique for a Clock Multiplier" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 4, pp. 647-651, April 2000, doi: .
Abstract: This paper describes a jitter suppression technique for a clock multiplier IC that uses a phase-locked loop (PLL). It is shown that the jitter cutoff frequency of the jitter transfer function can be greatly improved by adding a surface acoustic wave (SAW) filter whose center frequency equals the input frequency. The jitter transfer function is mainly determined by the characteristics of the SAW filter. Therefore, the clock multiplier IC can be set at a high loop gain to minimize the jitter generation without increasing the jitter cutoff frequency. The use of a clock multiplier IC that was fabricated with Si bipolar technology and a SAW filter with the center frequency of 155.52 MHz and a quality (Q) factor of 1500 results in a very low jitter generation of 3.5 mUI rms and an extremely low jitter cutoff frequency of about 50 kHz when the clock multiplier converts a clock frequency of 155.52 MHz into a 2.48832-GHz signal.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_4_647/_p
부
@ARTICLE{e83-c_4_647,
author={Kiyoshi ISHII, Keiji KISHINE, Haruhiko ICHINO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Jitter Suppression Technique for a Clock Multiplier},
year={2000},
volume={E83-C},
number={4},
pages={647-651},
abstract={This paper describes a jitter suppression technique for a clock multiplier IC that uses a phase-locked loop (PLL). It is shown that the jitter cutoff frequency of the jitter transfer function can be greatly improved by adding a surface acoustic wave (SAW) filter whose center frequency equals the input frequency. The jitter transfer function is mainly determined by the characteristics of the SAW filter. Therefore, the clock multiplier IC can be set at a high loop gain to minimize the jitter generation without increasing the jitter cutoff frequency. The use of a clock multiplier IC that was fabricated with Si bipolar technology and a SAW filter with the center frequency of 155.52 MHz and a quality (Q) factor of 1500 results in a very low jitter generation of 3.5 mUI rms and an extremely low jitter cutoff frequency of about 50 kHz when the clock multiplier converts a clock frequency of 155.52 MHz into a 2.48832-GHz signal.},
keywords={},
doi={},
ISSN={},
month={April},}
부
TY - JOUR
TI - A Jitter Suppression Technique for a Clock Multiplier
T2 - IEICE TRANSACTIONS on Electronics
SP - 647
EP - 651
AU - Kiyoshi ISHII
AU - Keiji KISHINE
AU - Haruhiko ICHINO
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2000
AB - This paper describes a jitter suppression technique for a clock multiplier IC that uses a phase-locked loop (PLL). It is shown that the jitter cutoff frequency of the jitter transfer function can be greatly improved by adding a surface acoustic wave (SAW) filter whose center frequency equals the input frequency. The jitter transfer function is mainly determined by the characteristics of the SAW filter. Therefore, the clock multiplier IC can be set at a high loop gain to minimize the jitter generation without increasing the jitter cutoff frequency. The use of a clock multiplier IC that was fabricated with Si bipolar technology and a SAW filter with the center frequency of 155.52 MHz and a quality (Q) factor of 1500 results in a very low jitter generation of 3.5 mUI rms and an extremely low jitter cutoff frequency of about 50 kHz when the clock multiplier converts a clock frequency of 155.52 MHz into a 2.48832-GHz signal.
ER -