The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
0.22mm 피치의 스트라이프 격벽을 갖는 24전극 표면 방전 AC-PDP에 대한 프라이밍 효과를 연구합니다. 리셋펄스와 어드레스펄스의 간격을 20㎲ 이내로 유지함으로써 데이터펄스 전압을 낮추는 동시에 프라이밍 효과로 인해 데이터펄스 폭을 좁힐 수 있는 것으로 나타났다. PDP에 프라이밍된 어드레싱 기법을 적용하여 데이터 펄스 전압과 스캔 펄스 폭이 1 µs일 때 데이터 펄스 전압을 0.33 V로 줄였습니다. 또는 데이터 펄스 전압이 56V일 때 데이터 펄스 폭을 69μs로 좁힐 수 있습니다. TV 필드 시간의 12%를 XNUMX개 서브 필드의 표시 기간에 할당하여 고휘도 표시를 보장할 수 있습니다.
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부
Makoto ISHII, Tomokazu SHIGA, Kiyoshi IGARASHI, Shigeo MIKOSHIBA, "A Study on a Priming Effect in AC-PDPs and Its Application to Low Voltage and High Speed Addressing" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 11, pp. 1673-1678, November 2001, doi: .
Abstract: A priming effect is studied for a three-electrode, surface-discharge AC-PDP, which has stripe barrier ribs of 0.22 mm pitch. It was found that by keeping the interval between the reset and address pulses within 24 µs, the data pulse voltage can be reduced while the data pulse width can be narrowed due to the priming effect. By adopting the primed addressing technique to the PDP, the data pulse voltage was reduced to 20 V when the data and scan pulse widths were 1 µs. Alternatively, the data pulse width could be narrowed to 0.33 µs when the data pulse voltage was 56 V. 69% of the TV field time could be assigned for the display periods with 12 sub-fields, assuring high luminance display.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_11_1673/_p
부
@ARTICLE{e84-c_11_1673,
author={Makoto ISHII, Tomokazu SHIGA, Kiyoshi IGARASHI, Shigeo MIKOSHIBA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Study on a Priming Effect in AC-PDPs and Its Application to Low Voltage and High Speed Addressing},
year={2001},
volume={E84-C},
number={11},
pages={1673-1678},
abstract={A priming effect is studied for a three-electrode, surface-discharge AC-PDP, which has stripe barrier ribs of 0.22 mm pitch. It was found that by keeping the interval between the reset and address pulses within 24 µs, the data pulse voltage can be reduced while the data pulse width can be narrowed due to the priming effect. By adopting the primed addressing technique to the PDP, the data pulse voltage was reduced to 20 V when the data and scan pulse widths were 1 µs. Alternatively, the data pulse width could be narrowed to 0.33 µs when the data pulse voltage was 56 V. 69% of the TV field time could be assigned for the display periods with 12 sub-fields, assuring high luminance display.},
keywords={},
doi={},
ISSN={},
month={November},}
부
TY - JOUR
TI - A Study on a Priming Effect in AC-PDPs and Its Application to Low Voltage and High Speed Addressing
T2 - IEICE TRANSACTIONS on Electronics
SP - 1673
EP - 1678
AU - Makoto ISHII
AU - Tomokazu SHIGA
AU - Kiyoshi IGARASHI
AU - Shigeo MIKOSHIBA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2001
AB - A priming effect is studied for a three-electrode, surface-discharge AC-PDP, which has stripe barrier ribs of 0.22 mm pitch. It was found that by keeping the interval between the reset and address pulses within 24 µs, the data pulse voltage can be reduced while the data pulse width can be narrowed due to the priming effect. By adopting the primed addressing technique to the PDP, the data pulse voltage was reduced to 20 V when the data and scan pulse widths were 1 µs. Alternatively, the data pulse width could be narrowed to 0.33 µs when the data pulse voltage was 56 V. 69% of the TV field time could be assigned for the display periods with 12 sub-fields, assuring high luminance display.
ER -