The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
많은 SoC 문제가 명백해졌기 때문에 미래의 전자 시스템은 SoC(System-on-a-Chip)만으로는 구축될 수 없습니다. 더 큰 다이 크기로 인한 상대적으로 낮은 수율과 다양한 종류의 기술을 내장하기 위한 프로세스 개발에 대한 막대한 투자가 문제 중 일부입니다. 대신, 전자 시스템 구축에 있어 실행 가능한 솔루션으로서 슈퍼커넥트 기술이 더욱 중요해지고 있습니다. 슈퍼커넥트는 별도로 제작 및 테스트된 칩을 인쇄회로기판이 아닌 직접 연결하여 고성능이면서도 저렴한 전자 시스템을 구성하며 약 10미크론 수준의 설계 규칙을 사용할 수 있습니다. 인터포저를 사용한 System-in-a-Package 및 적층형 칩은 슈퍼커넥트를 구현한 것입니다. 슈퍼커넥트는 글로벌 온칩 인터커넥트의 IR 드롭 문제와 RC 지연 문제를 완화하는 데에도 사용됩니다.
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Takayasu SAKURAI, "Superconnect Technology" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 12, pp. 1709-1716, December 2001, doi: .
Abstract: Future electronic systems can not be built only with System-on-a-Chip (SoC), since many SoC issues have become evident. Relatively low yield due to the larger die size and the huge investment in developing the process to embed different kinds of technologies are some of the issues. Instead, superconnect technology is getting more important as a viable solution in building electronic systems. The superconnect connects separately built and tested chips not by the printed circuit board but rather directly to construct high-performance yet low-cost electronic systems and may use around 10 micron level design rules. System-in-a-Package and stacked chips using interposers are some realization of the superconnect. The superconnect will also be used to mitigate IR-drop problems and RC delay problems in global on-chip interconnect.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_12_1709/_p
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@ARTICLE{e84-c_12_1709,
author={Takayasu SAKURAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Superconnect Technology},
year={2001},
volume={E84-C},
number={12},
pages={1709-1716},
abstract={Future electronic systems can not be built only with System-on-a-Chip (SoC), since many SoC issues have become evident. Relatively low yield due to the larger die size and the huge investment in developing the process to embed different kinds of technologies are some of the issues. Instead, superconnect technology is getting more important as a viable solution in building electronic systems. The superconnect connects separately built and tested chips not by the printed circuit board but rather directly to construct high-performance yet low-cost electronic systems and may use around 10 micron level design rules. System-in-a-Package and stacked chips using interposers are some realization of the superconnect. The superconnect will also be used to mitigate IR-drop problems and RC delay problems in global on-chip interconnect.},
keywords={},
doi={},
ISSN={},
month={December},}
부
TY - JOUR
TI - Superconnect Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 1709
EP - 1716
AU - Takayasu SAKURAI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2001
AB - Future electronic systems can not be built only with System-on-a-Chip (SoC), since many SoC issues have become evident. Relatively low yield due to the larger die size and the huge investment in developing the process to embed different kinds of technologies are some of the issues. Instead, superconnect technology is getting more important as a viable solution in building electronic systems. The superconnect connects separately built and tested chips not by the printed circuit board but rather directly to construct high-performance yet low-cost electronic systems and may use around 10 micron level design rules. System-in-a-Package and stacked chips using interposers are some realization of the superconnect. The superconnect will also be used to mitigate IR-drop problems and RC delay problems in global on-chip interconnect.
ER -