The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
단일 칩 MPEG-2 비디오, 오디오 및 시스템 인코더 LSI가 개발되었습니다. MPEG-2 422P@ML 비디오 인코딩, 2채널 Dolby Digital 또는 MPEG-1 오디오 인코딩, 다중화된 전송 스트림(TS) 또는 프로그램 스트림(PS)을 생성하는 시스템 인코딩을 동시에 실시간 처리합니다. 고성능 VLIW 미디어 프로세서 D30V와 유선 비디오 처리 회로를 결합한 고급 하이브리드 아키텍처가 채택되어 높은 유연성과 엄청난 계산 능력에 대한 요구를 모두 충족합니다. 단일 D30V를 사용하여 실시간 동시 처리를 달성하기 위해 비동기 비디오, 오디오 및 시스템 인코딩 프로세스에 대한 적응형 작업 우선 순위 제어를 계층적으로 관리하는 통합 제어 방식이 새로 제안되었습니다. 넓은 범위의 검색을 위한 CME(Coarse ME Core)와 정밀한 검색을 위한 FME(Fine ME Core)로 구성된 듀얼 전용 모션 추정 코어를 통합하여 적은 양의 하드웨어를 사용하면서 높은 화질을 구현합니다. 이러한 기능을 채택하여 0.25미크론 4층 금속 CMOS 기술을 사용하여 단일 칩 인코더를 제작하고 14.2mm 칩에 통합했습니다.
Tetsuya MATSUMURA
Satoshi KUMAKI
Hiroshi SEGAWA
Kazuya ISHIHARA
Atsuo HANAMI
Yoshinori MATSUURA
Stefan SCOTZNIOVSKY
Hidehiro TAKATA
Akira YAMADA
Shu MURAYAMA
Tetsuro WADA
Hideo OHIRA
Toshiaki SHIMADA
Ken-ichi ASANO
Toyohiko YOSHIDA
Masahiko YOSHIMOTO
Koji TSUCHIHASHI
Yasutaka HORIBA
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Tetsuya MATSUMURA, Satoshi KUMAKI, Hiroshi SEGAWA, Kazuya ISHIHARA, Atsuo HANAMI, Yoshinori MATSUURA, Stefan SCOTZNIOVSKY, Hidehiro TAKATA, Akira YAMADA, Shu MURAYAMA, Tetsuro WADA, Hideo OHIRA, Toshiaki SHIMADA, Ken-ichi ASANO, Toyohiko YOSHIDA, Masahiko YOSHIMOTO, Koji TSUCHIHASHI, Yasutaka HORIBA, "A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162 MHz Media-Processor Core and Dual Motion Estimation Cores" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 1, pp. 108-122, January 2001, doi: .
Abstract: A single-chip MPEG-2 video, audio, and system encoder LSI has been developed. It performs concurrent real-time processing of MPEG-2 422P@ML video encoding, 2-channel Dolby Digital or MPEG-1 audio encoding, and system encoding that generates a multiplexed transport stream (TS) or a program stream (PS). Advanced hybrid architecture, which combines a high performance VLIW media-processor D30V and hardwired video processing circuits, has been adopted to satisfy the demands of both high flexibility and enormous computational capability. A unified control scheme has been newly proposed that hierarchically manages adaptive task priority control over asynchronous video, audio, and system encoding processes in order to achieve real-time concurrent processing using a single D30V. Dual dedicated motion estimation cores consisting of a coarse ME core (CME) for wide range searches and a fine ME core (FME) for precise searches have been integrated to produce high picture quality while using a small amount of hardware. Adopting these features, a single-chip encoder has been fabricated using 0.25-micron 4-layer metal CMOS technology, and integrated into a 14.2 mm
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_1_108/_p
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@ARTICLE{e84-c_1_108,
author={Tetsuya MATSUMURA, Satoshi KUMAKI, Hiroshi SEGAWA, Kazuya ISHIHARA, Atsuo HANAMI, Yoshinori MATSUURA, Stefan SCOTZNIOVSKY, Hidehiro TAKATA, Akira YAMADA, Shu MURAYAMA, Tetsuro WADA, Hideo OHIRA, Toshiaki SHIMADA, Ken-ichi ASANO, Toyohiko YOSHIDA, Masahiko YOSHIMOTO, Koji TSUCHIHASHI, Yasutaka HORIBA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162 MHz Media-Processor Core and Dual Motion Estimation Cores},
year={2001},
volume={E84-C},
number={1},
pages={108-122},
abstract={A single-chip MPEG-2 video, audio, and system encoder LSI has been developed. It performs concurrent real-time processing of MPEG-2 422P@ML video encoding, 2-channel Dolby Digital or MPEG-1 audio encoding, and system encoding that generates a multiplexed transport stream (TS) or a program stream (PS). Advanced hybrid architecture, which combines a high performance VLIW media-processor D30V and hardwired video processing circuits, has been adopted to satisfy the demands of both high flexibility and enormous computational capability. A unified control scheme has been newly proposed that hierarchically manages adaptive task priority control over asynchronous video, audio, and system encoding processes in order to achieve real-time concurrent processing using a single D30V. Dual dedicated motion estimation cores consisting of a coarse ME core (CME) for wide range searches and a fine ME core (FME) for precise searches have been integrated to produce high picture quality while using a small amount of hardware. Adopting these features, a single-chip encoder has been fabricated using 0.25-micron 4-layer metal CMOS technology, and integrated into a 14.2 mm
keywords={},
doi={},
ISSN={},
month={January},}
부
TY - JOUR
TI - A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162 MHz Media-Processor Core and Dual Motion Estimation Cores
T2 - IEICE TRANSACTIONS on Electronics
SP - 108
EP - 122
AU - Tetsuya MATSUMURA
AU - Satoshi KUMAKI
AU - Hiroshi SEGAWA
AU - Kazuya ISHIHARA
AU - Atsuo HANAMI
AU - Yoshinori MATSUURA
AU - Stefan SCOTZNIOVSKY
AU - Hidehiro TAKATA
AU - Akira YAMADA
AU - Shu MURAYAMA
AU - Tetsuro WADA
AU - Hideo OHIRA
AU - Toshiaki SHIMADA
AU - Ken-ichi ASANO
AU - Toyohiko YOSHIDA
AU - Masahiko YOSHIMOTO
AU - Koji TSUCHIHASHI
AU - Yasutaka HORIBA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2001
AB - A single-chip MPEG-2 video, audio, and system encoder LSI has been developed. It performs concurrent real-time processing of MPEG-2 422P@ML video encoding, 2-channel Dolby Digital or MPEG-1 audio encoding, and system encoding that generates a multiplexed transport stream (TS) or a program stream (PS). Advanced hybrid architecture, which combines a high performance VLIW media-processor D30V and hardwired video processing circuits, has been adopted to satisfy the demands of both high flexibility and enormous computational capability. A unified control scheme has been newly proposed that hierarchically manages adaptive task priority control over asynchronous video, audio, and system encoding processes in order to achieve real-time concurrent processing using a single D30V. Dual dedicated motion estimation cores consisting of a coarse ME core (CME) for wide range searches and a fine ME core (FME) for precise searches have been integrated to produce high picture quality while using a small amount of hardware. Adopting these features, a single-chip encoder has been fabricated using 0.25-micron 4-layer metal CMOS technology, and integrated into a 14.2 mm
ER -