The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Nb 집적회로 제조 기술이 개발됐다. 제조 기술 개발에서 핵심 공정 단계는 미세한 Nb 전극을 형성하기 위한 에칭과 안정적인 절연층 형성입니다. 재현성과 신뢰성에 중점을 두고 표준 프로세스가 개발되었습니다. 이 공정에서는 기존의 반응성 이온 에칭과 RF 바이어스-스퍼터 증착이 사용됩니다. Nb 배선층 수는 0.9개이며, 접합 크기 2.3μm, 4.7μm, 2μm에 대해 임계 전류의 표준 편차(σ)는 각각 1.4%, 1%, 0.8%입니다. 통합 규모를 높이는 역량에 초점을 맞춘 고급 프로세스도 개발되었습니다. 전자 사이클로트론 공명 플라즈마 에칭과 기계적 연마 평탄화는 첨단 공정 기술로 개발되었습니다. Nb 배선층 수는 0.7개이며, 접합 크기 1.7μm, 2μm, 1.4μm에 대해 σ가 각각 1%, 10%, XNUMX%로 향상되었습니다. 통합 한계에 대해 논의되었으며 최대 접합 수는 XNUMX개 정도인 것으로 추정됩니다.5 및 107 각각 표준 및 고급 프로세스용입니다. 이러한 제조 기술을 이용하면 향후 수 M 비트 RAM과 같은 대규모 초전도 회로를 구현할 수 있습니다.
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Hideaki NUMATA, Shuichi TAHARA, "Fabrication Technology for Nb Integrated Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 1, pp. 2-8, January 2001, doi: .
Abstract: Fabrication technology for Nb integrated circuits has been developed. In developing fabrication technology, the key process steps are the etching to form fine Nb electrodes and the formation of reliable insulation layers. The standard process has been developed focusing on reproducibility and reliability. In the process, conventional reactive ion etching and RF bias-sputter deposition are used. The number of Nb wiring layers is two, and standard deviation (σ) of critical current is 0.9%, 2.3%, and 4.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. The advanced process has also been developed focusing on capability of increasing the integration scale. Electron-cyclotron-resonance plasma etching and mechanical polishing planarization have been developed as advanced process technology. The number of Nb wiring layers is three, and σ is improved to 0.8%, 0.7%, and 1.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. Integration limits are discussed and it is estimated that the maximum number of junctions is in the order of 105 and 107 for the standard and the advanced process, respectively. A large-scale superconducting circuit such as a several M-bit RAM can be realized in the future by using these fabrication technologies.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_1_2/_p
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@ARTICLE{e84-c_1_2,
author={Hideaki NUMATA, Shuichi TAHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fabrication Technology for Nb Integrated Circuits},
year={2001},
volume={E84-C},
number={1},
pages={2-8},
abstract={Fabrication technology for Nb integrated circuits has been developed. In developing fabrication technology, the key process steps are the etching to form fine Nb electrodes and the formation of reliable insulation layers. The standard process has been developed focusing on reproducibility and reliability. In the process, conventional reactive ion etching and RF bias-sputter deposition are used. The number of Nb wiring layers is two, and standard deviation (σ) of critical current is 0.9%, 2.3%, and 4.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. The advanced process has also been developed focusing on capability of increasing the integration scale. Electron-cyclotron-resonance plasma etching and mechanical polishing planarization have been developed as advanced process technology. The number of Nb wiring layers is three, and σ is improved to 0.8%, 0.7%, and 1.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. Integration limits are discussed and it is estimated that the maximum number of junctions is in the order of 105 and 107 for the standard and the advanced process, respectively. A large-scale superconducting circuit such as a several M-bit RAM can be realized in the future by using these fabrication technologies.},
keywords={},
doi={},
ISSN={},
month={January},}
부
TY - JOUR
TI - Fabrication Technology for Nb Integrated Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 2
EP - 8
AU - Hideaki NUMATA
AU - Shuichi TAHARA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2001
AB - Fabrication technology for Nb integrated circuits has been developed. In developing fabrication technology, the key process steps are the etching to form fine Nb electrodes and the formation of reliable insulation layers. The standard process has been developed focusing on reproducibility and reliability. In the process, conventional reactive ion etching and RF bias-sputter deposition are used. The number of Nb wiring layers is two, and standard deviation (σ) of critical current is 0.9%, 2.3%, and 4.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. The advanced process has also been developed focusing on capability of increasing the integration scale. Electron-cyclotron-resonance plasma etching and mechanical polishing planarization have been developed as advanced process technology. The number of Nb wiring layers is three, and σ is improved to 0.8%, 0.7%, and 1.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. Integration limits are discussed and it is estimated that the maximum number of junctions is in the order of 105 and 107 for the standard and the advanced process, respectively. A large-scale superconducting circuit such as a several M-bit RAM can be realized in the future by using these fabrication technologies.
ER -