The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
우리는 업/다운 카운터와 디지털-아날로그(D/A) 변환기로 구성된 디지털 FLL(flux-locked-loop) 회로를 갖춘 디지털 이중 이완 발진 SQUID(DROS)를 제시합니다. 업/다운 카운터는 4상 전원 시스템으로 작동하는 4JL(jucntion logic) 게이트를 사용하여 설계되었습니다. D/A 변환기는 R-2R 래더형 D/A 변환기를 사용하여 설계되었습니다. 우리는 2비트 리플 업/다운 카운터 및 D/A 변환기와 결합된 디지털 FLL 회로를 사용하여 디지털 DROS의 동적 동작을 시뮬레이션했습니다. 시뮬레이션 결과는 올바른 자속 고정 동작과 5의 높은 슬루율을 보여줍니다.7Φ0/s는 디지털 DROS입니다.
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부
Hiroaki MYOREN, Mitsunori NAKAMURA, Takeshi IIZUKA, Susumu TAKADA, "Proposal of a Digital Double Relaxation Oscillation SQUID" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 1, pp. 49-54, January 2001, doi: .
Abstract: We present a digital double relaxation oscillation SQUID (DROS) with a digital flux-locked-loop (FLL) circuit consisting of an up/down counter and a digital-to-analog (D/A) converter. The up/down counter was designed using 4 jucntion logic (4JL) gates operated with a 2-phase power system. The D/A converter was designed using an R-2R ladder-type D/A converter. We simulated the dynamic behavior of the digital DROS with a digital FLL circuit combined with the 5-bit ripple up/down counter and the D/A converter. Simulation results show correct flux-locked behavior and a high slew rate of 107Φ0/s for the digital DROS.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_1_49/_p
부
@ARTICLE{e84-c_1_49,
author={Hiroaki MYOREN, Mitsunori NAKAMURA, Takeshi IIZUKA, Susumu TAKADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Proposal of a Digital Double Relaxation Oscillation SQUID},
year={2001},
volume={E84-C},
number={1},
pages={49-54},
abstract={We present a digital double relaxation oscillation SQUID (DROS) with a digital flux-locked-loop (FLL) circuit consisting of an up/down counter and a digital-to-analog (D/A) converter. The up/down counter was designed using 4 jucntion logic (4JL) gates operated with a 2-phase power system. The D/A converter was designed using an R-2R ladder-type D/A converter. We simulated the dynamic behavior of the digital DROS with a digital FLL circuit combined with the 5-bit ripple up/down counter and the D/A converter. Simulation results show correct flux-locked behavior and a high slew rate of 107Φ0/s for the digital DROS.},
keywords={},
doi={},
ISSN={},
month={January},}
부
TY - JOUR
TI - Proposal of a Digital Double Relaxation Oscillation SQUID
T2 - IEICE TRANSACTIONS on Electronics
SP - 49
EP - 54
AU - Hiroaki MYOREN
AU - Mitsunori NAKAMURA
AU - Takeshi IIZUKA
AU - Susumu TAKADA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2001
AB - We present a digital double relaxation oscillation SQUID (DROS) with a digital flux-locked-loop (FLL) circuit consisting of an up/down counter and a digital-to-analog (D/A) converter. The up/down counter was designed using 4 jucntion logic (4JL) gates operated with a 2-phase power system. The D/A converter was designed using an R-2R ladder-type D/A converter. We simulated the dynamic behavior of the digital DROS with a digital FLL circuit combined with the 5-bit ripple up/down counter and the D/A converter. Simulation results show correct flux-locked behavior and a high slew rate of 107Φ0/s for the digital DROS.
ER -