The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
5.6 GOPS/1.4 GFLOPS 350MHz, 0.18방향 VLIW(Very Long Instruction Word) 마이크로프로세서는 16μm 50층 금속 CMOS 프로세스의 임베디드 애플리케이션용으로 개발되었습니다. 이 프로세서는 양방향 정수 파이프라인과 양방향 부동/미디어 파이프라인을 갖추고 있습니다. 각 플로팅 파이프라인과 미디어 파이프라인에는 각각 6.7병렬 및 7.5병렬 SIMD(단일 명령어 다중 데이터) 메커니즘이 있습니다. 프로세서에는 각각 크기가 XNUMXKB이고 XNUMX방향 세트 연관을 갖는 별도의 명령 및 데이터 캐시가 있습니다. 데이터 캐시는 비차단 기술을 사용하며 두 개의 로드 명령을 병렬로 처리할 수 있습니다. 프로세서는 전력 최적화가 없는 프로세서에 비해 클록 순 전력이 약 XNUMX% 감소했습니다. XNUMXmm 면적에 XNUMX만 개의 트랜지스터 집적
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Hiroshi OKANO, Atsuhiro SUGA, Hideo MIYAKE, Yoshimasa TAKEBE, Yasuki NAKAMURA, Hiromasa TAKAHASHI, "A 350 MHz 5.6 GOPS/1.4 GFLOPS 4-Way VLIW Embedded Microprocessor" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 2, pp. 150-156, February 2001, doi: .
Abstract: A 5.6 GOPS/1.4 GFLOPS 350 MHz, four-way very long instruction word (VLIW) microprocessor is developed for embedded applications in a 0.18 µm five-layer-metal CMOS process. This processor features a two-way integer pipeline and two-way floating/media pipelines. Each floating pipeline and media pipeline has two-parallel and four-parallel single instruction multiple-data (SIMD) mechanisms, respectively. The processor has separate instruction and data caches, each of 16 KB in size and having four-way set associative. The data cache employs a non-blocking technique and can process two load instructions in parallel. The processor had about a 50% clock net power reduction compared with one without power optimization. 6.7 million transistors are integrated in an area of 7.5 mm
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_150/_p
부
@ARTICLE{e84-c_2_150,
author={Hiroshi OKANO, Atsuhiro SUGA, Hideo MIYAKE, Yoshimasa TAKEBE, Yasuki NAKAMURA, Hiromasa TAKAHASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 350 MHz 5.6 GOPS/1.4 GFLOPS 4-Way VLIW Embedded Microprocessor},
year={2001},
volume={E84-C},
number={2},
pages={150-156},
abstract={A 5.6 GOPS/1.4 GFLOPS 350 MHz, four-way very long instruction word (VLIW) microprocessor is developed for embedded applications in a 0.18 µm five-layer-metal CMOS process. This processor features a two-way integer pipeline and two-way floating/media pipelines. Each floating pipeline and media pipeline has two-parallel and four-parallel single instruction multiple-data (SIMD) mechanisms, respectively. The processor has separate instruction and data caches, each of 16 KB in size and having four-way set associative. The data cache employs a non-blocking technique and can process two load instructions in parallel. The processor had about a 50% clock net power reduction compared with one without power optimization. 6.7 million transistors are integrated in an area of 7.5 mm
keywords={},
doi={},
ISSN={},
month={February},}
부
TY - JOUR
TI - A 350 MHz 5.6 GOPS/1.4 GFLOPS 4-Way VLIW Embedded Microprocessor
T2 - IEICE TRANSACTIONS on Electronics
SP - 150
EP - 156
AU - Hiroshi OKANO
AU - Atsuhiro SUGA
AU - Hideo MIYAKE
AU - Yoshimasa TAKEBE
AU - Yasuki NAKAMURA
AU - Hiromasa TAKAHASHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - A 5.6 GOPS/1.4 GFLOPS 350 MHz, four-way very long instruction word (VLIW) microprocessor is developed for embedded applications in a 0.18 µm five-layer-metal CMOS process. This processor features a two-way integer pipeline and two-way floating/media pipelines. Each floating pipeline and media pipeline has two-parallel and four-parallel single instruction multiple-data (SIMD) mechanisms, respectively. The processor has separate instruction and data caches, each of 16 KB in size and having four-way set associative. The data cache employs a non-blocking technique and can process two load instructions in parallel. The processor had about a 50% clock net power reduction compared with one without power optimization. 6.7 million transistors are integrated in an area of 7.5 mm
ER -