The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
두 개의 멀티미디어 VLIW 프로세서 코어를 하드웨어 스트리밍 엔진과 통합하는 칩이 설명됩니다. 실시간 화상전화나 MPEG4 코덱을 구현할 수 있습니다. 각 프로세서 코어는 동일한 리소스를 가지며 메모리 및 시스템 I/O 인터페이스 장치를 공유합니다. 대칭 구조를 사용하면 제약 없이 두 프로세서 모두에서 애플리케이션을 실행할 수 있습니다. 멀티미디어 관련 애플리케이션을 가속화하기 위해 이 프로세서의 아키텍처에는 여러 가지 기능이 있습니다. RISC와 DSP의 기능을 통합하고 명령 세트를 확장하여 비디오 및 오디오 애플리케이션을 모두 가속화하고 효율적인 임베디드 메모리 시스템을 지원하여 빈번한 메모리 액세스가 필요한 멀티미디어 애플리케이션의 대역폭과 대기 시간을 모두 줄입니다. 칩 크기는 100mm입니다.2 700μm CMOS 표준 셀 기술에 60K 논리 게이트, 16KB RAM 및 0.25KB ROM을 포함하는 다이입니다. 65MHz 작동 주파수에서는 CIF 263프레임/초로 H.15 비디오 코딩을 처리할 수 있으며, 723.1% 처리 시간 할당으로 G.80 오디오 코딩을 처리할 수 있습니다.
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Jeong-Min KIM, Yun-Su SHIN, In-Gu HWANG, Kwang-Sun LEE, Sang-Il HAN, Sang-Gyu PARK, Soo-Ik CHAE, "A High-Performance Videophone Chip with Dual Multimedia VLIW Processor Cores" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 2, pp. 183-192, February 2001, doi: .
Abstract: A chip is described that integrates two multimedia VLIW processor cores with a hardware streaming engine. It can implement a real-time videophone, or an MPEG4 codec. Each processor core has identical resources, and shares the memory and system I/O interface units. With its symmetric structure, applications can be executed on either processor without constraints. To accelerate multimedia-specific applications, the architecture of this processor has several features. It merges the features of a RISC and a DSP, its instruction set is extended to accelerate both video and audio applications, and it supports an efficient embedded memory system, to reduce both the bandwidth and the latency for multimedia applications needing frequent memory accesses. The chip size will be 100 mm2 die that contains 700 K logic gates, 60 KB RAM, and 16 KB ROM, in a 0.25-µm CMOS standard cell technology. At 65 MHz operating frequency, it can process H.263 video coding at CIF 15 frames/sec, and G.723.1 audio coding with an 80% processing time allocation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_183/_p
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@ARTICLE{e84-c_2_183,
author={Jeong-Min KIM, Yun-Su SHIN, In-Gu HWANG, Kwang-Sun LEE, Sang-Il HAN, Sang-Gyu PARK, Soo-Ik CHAE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Performance Videophone Chip with Dual Multimedia VLIW Processor Cores},
year={2001},
volume={E84-C},
number={2},
pages={183-192},
abstract={A chip is described that integrates two multimedia VLIW processor cores with a hardware streaming engine. It can implement a real-time videophone, or an MPEG4 codec. Each processor core has identical resources, and shares the memory and system I/O interface units. With its symmetric structure, applications can be executed on either processor without constraints. To accelerate multimedia-specific applications, the architecture of this processor has several features. It merges the features of a RISC and a DSP, its instruction set is extended to accelerate both video and audio applications, and it supports an efficient embedded memory system, to reduce both the bandwidth and the latency for multimedia applications needing frequent memory accesses. The chip size will be 100 mm2 die that contains 700 K logic gates, 60 KB RAM, and 16 KB ROM, in a 0.25-µm CMOS standard cell technology. At 65 MHz operating frequency, it can process H.263 video coding at CIF 15 frames/sec, and G.723.1 audio coding with an 80% processing time allocation.},
keywords={},
doi={},
ISSN={},
month={February},}
부
TY - JOUR
TI - A High-Performance Videophone Chip with Dual Multimedia VLIW Processor Cores
T2 - IEICE TRANSACTIONS on Electronics
SP - 183
EP - 192
AU - Jeong-Min KIM
AU - Yun-Su SHIN
AU - In-Gu HWANG
AU - Kwang-Sun LEE
AU - Sang-Il HAN
AU - Sang-Gyu PARK
AU - Soo-Ik CHAE
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - A chip is described that integrates two multimedia VLIW processor cores with a hardware streaming engine. It can implement a real-time videophone, or an MPEG4 codec. Each processor core has identical resources, and shares the memory and system I/O interface units. With its symmetric structure, applications can be executed on either processor without constraints. To accelerate multimedia-specific applications, the architecture of this processor has several features. It merges the features of a RISC and a DSP, its instruction set is extended to accelerate both video and audio applications, and it supports an efficient embedded memory system, to reduce both the bandwidth and the latency for multimedia applications needing frequent memory accesses. The chip size will be 100 mm2 die that contains 700 K logic gates, 60 KB RAM, and 16 KB ROM, in a 0.25-µm CMOS standard cell technology. At 65 MHz operating frequency, it can process H.263 video coding at CIF 15 frames/sec, and G.723.1 audio coding with an 80% processing time allocation.
ER -