The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 블록 매칭 모션 추정을 위한 향상된 다중 해상도 망원 검색 알고리즘(MRTlcSA)에 대해 설명합니다. 알고리즘은 전체 및 감소된 비트 해상도의 이미지를 사용하고 모션 트랙 및 적응형 검색 창 전략을 사용합니다. 시뮬레이션 결과는 제안된 알고리즘이 계산 복잡도가 낮고 좋은 이미지 품질을 달성한다는 것을 보여줍니다. 우리는 데이터 경로가 분할된 시스톨릭 아키텍처 기반 검색 엔진을 개발했습니다. 비트 해상도가 낮은 경우에는 작업 병렬성을 향상시켜 처리량을 높입니다. 새로운 모션 추정기는 낮은 클럭 주파수와 낮은 공급 전압에서 작동하므로 전력 소비가 낮습니다.
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Wujian ZHANG, Runde ZHOU, Tsunehachi ISHITANI, Ryota KASAI, Toshio KONDO, "Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 3, pp. 399-409, March 2001, doi: .
Abstract: This paper describes an improved multiresolution telescopic search algorithm (MRTlcSA) for block-matching motion estimation. The algorithm uses images with full and reduced bit resolution, and uses motion-track and adaptive-search-window strategies. Simulation results show that the proposed algorithm has low computational complexity and achieves good image quality. We have developed a systolic-architecture-based search engine that has split data paths. In the case of low bit-resolution, the throughput is increased by enhancing the operating parallelism. The new motion estimator works at a low clock frequency and a low supply voltage, and therefore has low power consumption.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_3_399/_p
부
@ARTICLE{e84-c_3_399,
author={Wujian ZHANG, Runde ZHOU, Tsunehachi ISHITANI, Ryota KASAI, Toshio KONDO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images},
year={2001},
volume={E84-C},
number={3},
pages={399-409},
abstract={This paper describes an improved multiresolution telescopic search algorithm (MRTlcSA) for block-matching motion estimation. The algorithm uses images with full and reduced bit resolution, and uses motion-track and adaptive-search-window strategies. Simulation results show that the proposed algorithm has low computational complexity and achieves good image quality. We have developed a systolic-architecture-based search engine that has split data paths. In the case of low bit-resolution, the throughput is increased by enhancing the operating parallelism. The new motion estimator works at a low clock frequency and a low supply voltage, and therefore has low power consumption.},
keywords={},
doi={},
ISSN={},
month={March},}
부
TY - JOUR
TI - Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images
T2 - IEICE TRANSACTIONS on Electronics
SP - 399
EP - 409
AU - Wujian ZHANG
AU - Runde ZHOU
AU - Tsunehachi ISHITANI
AU - Ryota KASAI
AU - Toshio KONDO
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2001
AB - This paper describes an improved multiresolution telescopic search algorithm (MRTlcSA) for block-matching motion estimation. The algorithm uses images with full and reduced bit resolution, and uses motion-track and adaptive-search-window strategies. Simulation results show that the proposed algorithm has low computational complexity and achieves good image quality. We have developed a systolic-architecture-based search engine that has split data paths. In the case of low bit-resolution, the throughput is increased by enhancing the operating parallelism. The new motion estimator works at a low clock frequency and a low supply voltage, and therefore has low power consumption.
ER -