The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 문서에서는 디지털 가입자 루프 애플리케이션을 위한 8b 52MHz CMOS 하위 범위 아날로그-디지털 변환기(ADC)에 대해 설명합니다. 개선된 시간 인터리빙 아키텍처를 기반으로 제안된 ADC는 기존 이중 채널 범위 조정 ADC에서 일반적으로 관찰되는 유지 시간을 제거하여 처리량 속도를 50% 증가시킵니다. ADC는 잔여 신호 처리를 위해 백엔드 범위 조정 ADC에서 보간 기술을 사용하여 활성 다이 영역과 전력 소비를 최소화합니다. 플라즈마 유도 비교기 오프셋과 ADC의 다이 면적을 줄이기 위해 레이아웃 기술이 채택되었습니다. 0.8 µm CMOS 공정에서 제작 및 측정된 프로토타입 ADC는 다음보다 작은 비선형성을 나타냅니다.
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부
Sung-Ho LEE, Jung-Woong MOON, Seung-Hoon LEE, "An 8b 52 MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 4, pp. 470-474, April 2001, doi: .
Abstract: This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_4_470/_p
부
@ARTICLE{e84-c_4_470,
author={Sung-Ho LEE, Jung-Woong MOON, Seung-Hoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={An 8b 52 MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications},
year={2001},
volume={E84-C},
number={4},
pages={470-474},
abstract={This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than
keywords={},
doi={},
ISSN={},
month={April},}
부
TY - JOUR
TI - An 8b 52 MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 470
EP - 474
AU - Sung-Ho LEE
AU - Jung-Woong MOON
AU - Seung-Hoon LEE
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2001
AB - This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than
ER -