The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
완전히 통합된 저드롭아웃(LDO), 낮은 대기 전류 레귤레이터는 0.6μm CMOS 기술로 제작되었습니다. 낮고 높은 유효 직렬 저항(ESR) 커패시터로 안정적입니다. 동적 피드백(DNFB) 바이어스 기술은 우수한 과도 응답을 유지하면서 우수한 전류 효율을 달성하도록 LDO의 오류 증폭기를 바이어스하는 데 사용됩니다. 동적 피드백이 있는 LDO 레귤레이터와 없는 LDO 레귤레이터의 성능을 비교하기 위해 오류 증폭기는 큰 바이어스 전류(LC), 작은 바이어스 전류(SC) 및 스위치를 사용하여 동적 피드백 전류가 있는 바이어스를 갖도록 구성됩니다. 측정 결과는 DNFB의 라인 및 부하 규정이 각각 0.145%/V 및 11ppm/mA임을 보여줍니다. 또한 부하 전류가 33mA에서 0mA로 전환될 때 SC LDO에 비해 정착 시간과 전압 강하가 약 50% 감소합니다. 드롭아웃 전압을 줄이기 위해 DNFB 기반의 드롭아웃 감소 회로도 LDO 출력 PMOS의 문턱 전압을 낮추도록 설계되었습니다. 측정된 드롭아웃 감소는 8.1mV이며 이는 DNFB의 더 큰 피드백 비율로 더 감소될 수 있습니다. 이 LDO의 대기 전류는 59.4μA로 측정되었으며 이 LDO는 250V의 입력 전압에서 3.6mA의 최대 출력 전류를 제공할 수 있습니다. 이 LDO의 활성 영역은 760μm입니다.
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부
Yen-Shyung SHYU, Jiin-Chuan WU, "A 60 µA Quiscent Current, 250 mA CMOS Low Dropout Regulator" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 5, pp. 693-703, May 2001, doi: .
Abstract: A fully integrated Low Dropout (LDO), low quiescent current regulator has been fabricated in a 0.6 µm CMOS technology. It is stable with low and high effective series resistance (ESR) capacitors. A dynamic feedback (DNFB) bias technique is used to bias the error amplifier in the LDO such that good current efficiency is achieved while maintaining a good transient response. In order to compare the performance of the LDO regulators with and without dynamic feedback, the error amplifiers are configured to have a large bias current (LC), a small bias current (SC) and a bias with dynamic feedback current using switches. The measurement results show that DNFB's line and load regulations are 0.145%/V and 11 ppm/mA, respectively. Besides, there is about 33% reduction in settling time and voltage drop compared with SC LDO when load current is switching from 0 mA to 50 mA. In order to reduce the dropout voltage, a dropout reduction circuitry based on DNFB is also designed to reduce the threshold voltage of LDO's output PMOS. The measured dropout reduction is 8.1 mV which can be further reduced by a larger feedback ratio in DNFB. The quiescent current of this LDO is measured to be 59.4 µ A and this LDO can provide a maximum output current of 250 mA at an input voltage of 3.6 V. The active area of this LDO is 760 µ m
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_5_693/_p
부
@ARTICLE{e84-c_5_693,
author={Yen-Shyung SHYU, Jiin-Chuan WU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 60 µA Quiscent Current, 250 mA CMOS Low Dropout Regulator},
year={2001},
volume={E84-C},
number={5},
pages={693-703},
abstract={A fully integrated Low Dropout (LDO), low quiescent current regulator has been fabricated in a 0.6 µm CMOS technology. It is stable with low and high effective series resistance (ESR) capacitors. A dynamic feedback (DNFB) bias technique is used to bias the error amplifier in the LDO such that good current efficiency is achieved while maintaining a good transient response. In order to compare the performance of the LDO regulators with and without dynamic feedback, the error amplifiers are configured to have a large bias current (LC), a small bias current (SC) and a bias with dynamic feedback current using switches. The measurement results show that DNFB's line and load regulations are 0.145%/V and 11 ppm/mA, respectively. Besides, there is about 33% reduction in settling time and voltage drop compared with SC LDO when load current is switching from 0 mA to 50 mA. In order to reduce the dropout voltage, a dropout reduction circuitry based on DNFB is also designed to reduce the threshold voltage of LDO's output PMOS. The measured dropout reduction is 8.1 mV which can be further reduced by a larger feedback ratio in DNFB. The quiescent current of this LDO is measured to be 59.4 µ A and this LDO can provide a maximum output current of 250 mA at an input voltage of 3.6 V. The active area of this LDO is 760 µ m
keywords={},
doi={},
ISSN={},
month={May},}
부
TY - JOUR
TI - A 60 µA Quiscent Current, 250 mA CMOS Low Dropout Regulator
T2 - IEICE TRANSACTIONS on Electronics
SP - 693
EP - 703
AU - Yen-Shyung SHYU
AU - Jiin-Chuan WU
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2001
AB - A fully integrated Low Dropout (LDO), low quiescent current regulator has been fabricated in a 0.6 µm CMOS technology. It is stable with low and high effective series resistance (ESR) capacitors. A dynamic feedback (DNFB) bias technique is used to bias the error amplifier in the LDO such that good current efficiency is achieved while maintaining a good transient response. In order to compare the performance of the LDO regulators with and without dynamic feedback, the error amplifiers are configured to have a large bias current (LC), a small bias current (SC) and a bias with dynamic feedback current using switches. The measurement results show that DNFB's line and load regulations are 0.145%/V and 11 ppm/mA, respectively. Besides, there is about 33% reduction in settling time and voltage drop compared with SC LDO when load current is switching from 0 mA to 50 mA. In order to reduce the dropout voltage, a dropout reduction circuitry based on DNFB is also designed to reduce the threshold voltage of LDO's output PMOS. The measured dropout reduction is 8.1 mV which can be further reduced by a larger feedback ratio in DNFB. The quiescent current of this LDO is measured to be 59.4 µ A and this LDO can provide a maximum output current of 250 mA at an input voltage of 3.6 V. The active area of this LDO is 760 µ m
ER -