The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
1T2C형 강유전체 메모리 셀은 동일한 면적의 강유전체 커패시터 XNUMX개를 SiOXNUMX로 일반 MOSFET의 게이트에 연결한 것입니다.2/Si 인터페이스를 제작하고 특성화했습니다. SPICE 시뮬레이션을 이용하여 다양한 소자 파라미터와 메모리 셀 특성 간의 관계를 조사했습니다. 시뮬레이션 결과에서 메모리 윈도우는 소자 매개변수에 따라 크게 변화하는 것으로 나타났습니다. 이는 메모리 셀의 동작 전압이 이러한 매개변수에 의해 잘 제어될 수 있음을 의미합니다. 제작된 셀은 Pt/SBT/Pt/Ti/SiO의 적층형 게이트 구조로 구성된다.2/Si와 MOS 커패시터의 면적비(SO)를 강유전체 커패시터(SF) of 6 또는 10. 비휘발성 메모리 동작이 확인되었으며, 획득된 메모리 창은 시뮬레이션 결과와 질적으로 일치했습니다. 또한, 판독 동작 시 전류 온/오프 비율은 3배 이상 크고, 데이터 보유 시간은 6배 이상인 것으로 나타났다.
강유전체 게이트 FET, 보유, 1T2C, 메모리 창, 임계 전압
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Satoru OGASAWARA, Sung-Min YOON, Hiroshi ISHIWARA, "Fabrication and Characterization of 1T2C-Type Ferroelectric Memory Cell" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 6, pp. 771-776, June 2001, doi: .
Abstract: A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO2/Si interface, was fabricated and characterized. The relations between various device parameters and characteristics of memory cell were investigated by using SPICE simulation. It was found from the simulation results that the memory window significantly changed by the device parameters, which means that the operation voltage of the memory cell can be well controlled by these parameters. The fabricated cell is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO2/Si with the area ratio of the MOS capacitor (SO) to the ferroelectric capacitor (SF) of 6 or 10. Nonvolatile memory operation was confirmed, and the obtained memory window coincided with the simulated results qualitatively. Furthermore, the current on/off ratio in the read-out operation was larger than 3-order-of magnitude and the data retention time was longer than 6
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_6_771/_p
부
@ARTICLE{e84-c_6_771,
author={Satoru OGASAWARA, Sung-Min YOON, Hiroshi ISHIWARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fabrication and Characterization of 1T2C-Type Ferroelectric Memory Cell},
year={2001},
volume={E84-C},
number={6},
pages={771-776},
abstract={A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO2/Si interface, was fabricated and characterized. The relations between various device parameters and characteristics of memory cell were investigated by using SPICE simulation. It was found from the simulation results that the memory window significantly changed by the device parameters, which means that the operation voltage of the memory cell can be well controlled by these parameters. The fabricated cell is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO2/Si with the area ratio of the MOS capacitor (SO) to the ferroelectric capacitor (SF) of 6 or 10. Nonvolatile memory operation was confirmed, and the obtained memory window coincided with the simulated results qualitatively. Furthermore, the current on/off ratio in the read-out operation was larger than 3-order-of magnitude and the data retention time was longer than 6
keywords={},
doi={},
ISSN={},
month={June},}
부
TY - JOUR
TI - Fabrication and Characterization of 1T2C-Type Ferroelectric Memory Cell
T2 - IEICE TRANSACTIONS on Electronics
SP - 771
EP - 776
AU - Satoru OGASAWARA
AU - Sung-Min YOON
AU - Hiroshi ISHIWARA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2001
AB - A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO2/Si interface, was fabricated and characterized. The relations between various device parameters and characteristics of memory cell were investigated by using SPICE simulation. It was found from the simulation results that the memory window significantly changed by the device parameters, which means that the operation voltage of the memory cell can be well controlled by these parameters. The fabricated cell is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO2/Si with the area ratio of the MOS capacitor (SO) to the ferroelectric capacitor (SF) of 6 or 10. Nonvolatile memory operation was confirmed, and the obtained memory window coincided with the simulated results qualitatively. Furthermore, the current on/off ratio in the read-out operation was larger than 3-order-of magnitude and the data retention time was longer than 6
ER -