The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
부하선 분석을 이용한 FET의 효율적인 대신호 모델링 방법을 제안하고, 이를 FET의 비선형 특성화에 적용합니다. 이 방법에서는 순간적인 드레인-소스 전압이 Vds(t) 및 드레인 소스 전류 Ids(t) 파형은 부하선 분석에 의해 결정되는 반면, FET의 대신호 등가 회로의 비선형 매개변수는 순간에 해당하는 한 기간 동안의 평균값으로 정의됩니다. Vds(t) and Ids(t). 출력 파워 (P아웃), 전력부가효율(θ)더하다), 이러한 FET의 등가회로를 이용하여 계산한 위상편차는 933.5MHz에서 측정한 결과와 잘 일치한다. 위상 편차 메커니즘은 FET의 대신호 등가 회로를 기반으로 설명되며 트랜스 컨덕턴스(gm), 드레인-소스 저항(Rds), 게이트-소스 커패시턴스(Cgs) 및 게이트 누출 저항(Rig) 양수 또는 음수 위상 편차에 기여합니다. 소신호와 대신호의 차이 S-매개변수(S11, S12, S21, S22)에 대해서도 논의하고 있습니다. 제안된 대신호 모델링 방법은 대신호 동작 조건에서 FET의 동작을 조사할 뿐만 아니라 고출력, 고효율, 저왜곡 증폭기의 설계에 유용할 것으로 판단된다.
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부
Yukio IKEDA, Kazutomi MORI, Masatoshi NAKAYAMA, Yasushi ITOH, Osami ISHIDA, Tadashi TAKAGI, "An Efficient Large-Signal Modeling Method Using Load-Line Analysis and Its Application to Non-linear Characterization of FET" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 7, pp. 875-880, July 2001, doi: .
Abstract: An efficient large-signal modeling method of FET using load-line analysis is proposed, and it is applied to non-linear characterization of FET. In this method, instantaneous drain-source voltage Vds(t) and drain-source current Ids(t) waveforms are determined by load-line analysis while non-linear parameters in a large-signal equivalent circuit of FET are defined as the average values over one period corresponding to instantaneous Vds(t) and Ids(t). Output power (Pout), power added efficiency (ηadd), and phase deviation calculated by using such an equivalent circuit of FET agree well with the measured results at 933.5 MHz. Phase deviation mechanism is explained based on the large-signal equivalent circuit of FET, and it is shown how non-linear parameters, such as trans-conductance (gm), drain-source resistance (Rds), gate-source capacitance (Cgs), and gate leak resistance (Rig) contribute to positive or negative phase deviations. The difference between small-signal and large-signal S-parameters (S11, S12, S21, S22) is also discussed. The proposed large-signal modeling method is considered to be useful for the design of high power, high efficiency, and low distortion amplifiers as well as the investigation of the behavior of FET in large-signal operating conditions.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_7_875/_p
부
@ARTICLE{e84-c_7_875,
author={Yukio IKEDA, Kazutomi MORI, Masatoshi NAKAYAMA, Yasushi ITOH, Osami ISHIDA, Tadashi TAKAGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Efficient Large-Signal Modeling Method Using Load-Line Analysis and Its Application to Non-linear Characterization of FET},
year={2001},
volume={E84-C},
number={7},
pages={875-880},
abstract={An efficient large-signal modeling method of FET using load-line analysis is proposed, and it is applied to non-linear characterization of FET. In this method, instantaneous drain-source voltage Vds(t) and drain-source current Ids(t) waveforms are determined by load-line analysis while non-linear parameters in a large-signal equivalent circuit of FET are defined as the average values over one period corresponding to instantaneous Vds(t) and Ids(t). Output power (Pout), power added efficiency (ηadd), and phase deviation calculated by using such an equivalent circuit of FET agree well with the measured results at 933.5 MHz. Phase deviation mechanism is explained based on the large-signal equivalent circuit of FET, and it is shown how non-linear parameters, such as trans-conductance (gm), drain-source resistance (Rds), gate-source capacitance (Cgs), and gate leak resistance (Rig) contribute to positive or negative phase deviations. The difference between small-signal and large-signal S-parameters (S11, S12, S21, S22) is also discussed. The proposed large-signal modeling method is considered to be useful for the design of high power, high efficiency, and low distortion amplifiers as well as the investigation of the behavior of FET in large-signal operating conditions.},
keywords={},
doi={},
ISSN={},
month={July},}
부
TY - JOUR
TI - An Efficient Large-Signal Modeling Method Using Load-Line Analysis and Its Application to Non-linear Characterization of FET
T2 - IEICE TRANSACTIONS on Electronics
SP - 875
EP - 880
AU - Yukio IKEDA
AU - Kazutomi MORI
AU - Masatoshi NAKAYAMA
AU - Yasushi ITOH
AU - Osami ISHIDA
AU - Tadashi TAKAGI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2001
AB - An efficient large-signal modeling method of FET using load-line analysis is proposed, and it is applied to non-linear characterization of FET. In this method, instantaneous drain-source voltage Vds(t) and drain-source current Ids(t) waveforms are determined by load-line analysis while non-linear parameters in a large-signal equivalent circuit of FET are defined as the average values over one period corresponding to instantaneous Vds(t) and Ids(t). Output power (Pout), power added efficiency (ηadd), and phase deviation calculated by using such an equivalent circuit of FET agree well with the measured results at 933.5 MHz. Phase deviation mechanism is explained based on the large-signal equivalent circuit of FET, and it is shown how non-linear parameters, such as trans-conductance (gm), drain-source resistance (Rds), gate-source capacitance (Cgs), and gate leak resistance (Rig) contribute to positive or negative phase deviations. The difference between small-signal and large-signal S-parameters (S11, S12, S21, S22) is also discussed. The proposed large-signal modeling method is considered to be useful for the design of high power, high efficiency, and low distortion amplifiers as well as the investigation of the behavior of FET in large-signal operating conditions.
ER -