The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
전력벽으로 인해 기술 확장이 어려워질 것입니다. 반면, 미래의 컴퓨터 및 통신 기술에서는 전력 소비를 더욱 줄여야 합니다. 새로운 에너지 효율적인 장치 기술이 아직 나오지 않았기 때문에 저전력 CMOS 설계에 도전해야 합니다. 이 문서에서는 디자이너가 CMOS 전력 절감을 위해 무엇을, 얼마나 할 수 있는지에 대해 설명합니다.
저전력 CMOS 설계, 낮은 전압, 임계 전압, 문턱하 누설 전류, 축소
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Tadahiro KURODA, "Low Power CMOS Design Challenges" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1021-1028, August 2001, doi: .
Abstract: Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1021/_p
부
@ARTICLE{e84-c_8_1021,
author={Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low Power CMOS Design Challenges},
year={2001},
volume={E84-C},
number={8},
pages={1021-1028},
abstract={Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.},
keywords={},
doi={},
ISSN={},
month={August},}
부
TY - JOUR
TI - Low Power CMOS Design Challenges
T2 - IEICE TRANSACTIONS on Electronics
SP - 1021
EP - 1028
AU - Tadahiro KURODA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.
ER -