The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
고전류 구동과 낮은 공급 전압 요구 사항을 모두 충족하는 스케일링된 CMOS를 실현하는 효과적인 방법은 변형된 Si와 같은 높은 이동도 채널을 도입하는 것입니다. 본 논문에서는 100nm 이하 Si CMOS 기술 노드에 적용할 수 있는 변형된 Si 채널, 변형된 SOI(Strained-Si-on-Insulator) MOSFET을 사용하는 새로운 장치 구조를 제안합니다. 스트레인드 SOI MOSFET의 장치 구조와 장점이 제시됩니다. 변형된 SOI MOSFET은 변형된 Si의 재성장과 SIMOX 기술을 결합하여 성공적으로 제조되었으며 n- 및 p-MOSFET는 범용보다 각각 1.6배 및 1.3배 더 높은 이동도를 갖는다는 것이 입증되었습니다. 또한 이동도를 더욱 높이고 완전히 공핍된 SOI MOSFET을 구현하는 데 필요한 Ge 함량이 높은 초박형 SGOI(SiGe-on-Insulator) 가상 기판은 더 낮은 Ge를 갖는 SGOI 구조의 산화를 통해 만들어질 수 있음이 입증되었습니다. 콘텐츠.
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Shin-ichi TAKAGI, Tomohisa MIZUNO, Naoharu SUGIYAMA, Tsutomu TEZUKA, Atsushi KUROBE, "Strained-Si-on-Insulator (Strained-SOI) MOSFETs--Concept, Structures and Device Characteristics" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1043-1050, August 2001, doi: .
Abstract: An effective way to realize scaled CMOS with both requirements of high current drive and low supply voltage is to introduce high mobility channel such as strained Si. This paper proposes a new device structure using the strained-Si channel, strained-Si-on-Insulator (strained-SOI) MOSFET, applicable to sub-100 nm Si CMOS technology nodes. The device structure and the advantages of strained-SOI MOSFETs are presented. It is demonstrated that strained-SOI MOSFETs are successfully fabricated by combining SIMOX technology with re-growth of strained Si and that n- and p-MOSFETs have mobility of 1.6 and 1.3 times higher than the universal one, respectively. Furthermore, it is also shown that ultra-thin SiGe-on-Insulator (SGOI) virtual substrates with higher Ge content, necessary to further increase mobility and to realize fully-depleted SOI MOSFETs, can be made by oxidation of SGOI structure with lower Ge content.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1043/_p
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@ARTICLE{e84-c_8_1043,
author={Shin-ichi TAKAGI, Tomohisa MIZUNO, Naoharu SUGIYAMA, Tsutomu TEZUKA, Atsushi KUROBE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Strained-Si-on-Insulator (Strained-SOI) MOSFETs--Concept, Structures and Device Characteristics},
year={2001},
volume={E84-C},
number={8},
pages={1043-1050},
abstract={An effective way to realize scaled CMOS with both requirements of high current drive and low supply voltage is to introduce high mobility channel such as strained Si. This paper proposes a new device structure using the strained-Si channel, strained-Si-on-Insulator (strained-SOI) MOSFET, applicable to sub-100 nm Si CMOS technology nodes. The device structure and the advantages of strained-SOI MOSFETs are presented. It is demonstrated that strained-SOI MOSFETs are successfully fabricated by combining SIMOX technology with re-growth of strained Si and that n- and p-MOSFETs have mobility of 1.6 and 1.3 times higher than the universal one, respectively. Furthermore, it is also shown that ultra-thin SiGe-on-Insulator (SGOI) virtual substrates with higher Ge content, necessary to further increase mobility and to realize fully-depleted SOI MOSFETs, can be made by oxidation of SGOI structure with lower Ge content.},
keywords={},
doi={},
ISSN={},
month={August},}
부
TY - JOUR
TI - Strained-Si-on-Insulator (Strained-SOI) MOSFETs--Concept, Structures and Device Characteristics
T2 - IEICE TRANSACTIONS on Electronics
SP - 1043
EP - 1050
AU - Shin-ichi TAKAGI
AU - Tomohisa MIZUNO
AU - Naoharu SUGIYAMA
AU - Tsutomu TEZUKA
AU - Atsushi KUROBE
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - An effective way to realize scaled CMOS with both requirements of high current drive and low supply voltage is to introduce high mobility channel such as strained Si. This paper proposes a new device structure using the strained-Si channel, strained-Si-on-Insulator (strained-SOI) MOSFET, applicable to sub-100 nm Si CMOS technology nodes. The device structure and the advantages of strained-SOI MOSFETs are presented. It is demonstrated that strained-SOI MOSFETs are successfully fabricated by combining SIMOX technology with re-growth of strained Si and that n- and p-MOSFETs have mobility of 1.6 and 1.3 times higher than the universal one, respectively. Furthermore, it is also shown that ultra-thin SiGe-on-Insulator (SGOI) virtual substrates with higher Ge content, necessary to further increase mobility and to realize fully-depleted SOI MOSFETs, can be made by oxidation of SGOI structure with lower Ge content.
ER -