The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
상당히 높은 온도에서 높은 전압 이득을 갖는 Si 단일 전자 트랜지스터는 수직 패턴 의존 산화에 의해 제조되었습니다. 이 방법을 사용하면 1aF 미만의 커패시턴스를 갖는 매우 작은 터널 접합을 자동으로 형성할 수 있습니다. 또한 얇은(수십 나노미터 두께) 게이트 산화물을 사용하면 아일랜드와 게이트의 강한 결합이 가능해지며, 이로 인해 게이트 정전용량이 접합 정전용량보다 커집니다. 27K에서 게이트 커패시턴스와 드레인 터널 커패시턴스의 비율에 따라 결정되는 반전 전압 이득이 일정한 드레인 전류 조건에서 3을 초과한다는 것이 입증되었습니다.
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Yukinori ONO, Kenji YAMAZAKI, Yasuo TAKAHASHI, "Si Single-Electron Transistors with High Voltage Gain" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1061-1065, August 2001, doi: .
Abstract: Si single-electron transistors with a high voltage gain at a considerably high temperature have been fabricated by vertical pattern-dependent oxidation. The method enables the automatic formation of very small tunnel junctions having capacitances of less than 1 aF. In addition, the use of a thin (a few ten nanometers thick) gate oxide allows a strong coupling of the island to the gate, which results in a gate capacitance larger than the junction capacitances. It is demonstrated at 27 K that an inverting voltage gain, which is governed by the ratio of the gate capacitance to the drain tunnel capacitance, exceeds 3 under constant drain current conditions.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1061/_p
부
@ARTICLE{e84-c_8_1061,
author={Yukinori ONO, Kenji YAMAZAKI, Yasuo TAKAHASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Si Single-Electron Transistors with High Voltage Gain},
year={2001},
volume={E84-C},
number={8},
pages={1061-1065},
abstract={Si single-electron transistors with a high voltage gain at a considerably high temperature have been fabricated by vertical pattern-dependent oxidation. The method enables the automatic formation of very small tunnel junctions having capacitances of less than 1 aF. In addition, the use of a thin (a few ten nanometers thick) gate oxide allows a strong coupling of the island to the gate, which results in a gate capacitance larger than the junction capacitances. It is demonstrated at 27 K that an inverting voltage gain, which is governed by the ratio of the gate capacitance to the drain tunnel capacitance, exceeds 3 under constant drain current conditions.},
keywords={},
doi={},
ISSN={},
month={August},}
부
TY - JOUR
TI - Si Single-Electron Transistors with High Voltage Gain
T2 - IEICE TRANSACTIONS on Electronics
SP - 1061
EP - 1065
AU - Yukinori ONO
AU - Kenji YAMAZAKI
AU - Yasuo TAKAHASHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - Si single-electron transistors with a high voltage gain at a considerably high temperature have been fabricated by vertical pattern-dependent oxidation. The method enables the automatic formation of very small tunnel junctions having capacitances of less than 1 aF. In addition, the use of a thin (a few ten nanometers thick) gate oxide allows a strong coupling of the island to the gate, which results in a gate capacitance larger than the junction capacitances. It is demonstrated at 27 K that an inverting voltage gain, which is governed by the ratio of the gate capacitance to the drain tunnel capacitance, exceeds 3 under constant drain current conditions.
ER -