The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
단일 전자 트랜지스터(SET)와 상보성 금속 산화물 반도체 전계 효과 트랜지스터(CMOSFET)의 하이브리드 논리 회로의 전력 소비를 계산했습니다. SET/CMOS 하이브리드 논리 회로는 SET 논리 트리와 CMOS 증폭기로 구성되며, 그 입력은 SET 논리 트리의 출력에 연결되며, CMOS 증폭기의 입력과 SET의 출력 사이의 상호 연결 커패시턴스가 감소하는 것으로 나타났습니다. 전력 소모를 줄이기 위해서는 로직 트리가 필수적이었습니다. 상호 연결 용량을 줄이기 위한 새로운 전략 풀다운 장치로 작동하는 SET 및 해당 보완 SET를 사용하여 논리 트리 구성 처음으로 제안했습니다. 결과적으로, 많은 양의 상호 연결 커패시턴스가 제거될 수 있었고 SET/CMOS 하이브리드의 전력 소비가 상당히 낮아졌습니다.
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Ken UCHIDA, Junji KOGA, Ryuji OHBA, Akira TORIUMI, "Power Consumption of Hybrid Circuits of Single-Electron Transistors and Complementary Metal-Oxide-Semiconductor Field-Effect Transistors" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1066-1070, August 2001, doi: .
Abstract: The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1066/_p
부
@ARTICLE{e84-c_8_1066,
author={Ken UCHIDA, Junji KOGA, Ryuji OHBA, Akira TORIUMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Power Consumption of Hybrid Circuits of Single-Electron Transistors and Complementary Metal-Oxide-Semiconductor Field-Effect Transistors},
year={2001},
volume={E84-C},
number={8},
pages={1066-1070},
abstract={The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.},
keywords={},
doi={},
ISSN={},
month={August},}
부
TY - JOUR
TI - Power Consumption of Hybrid Circuits of Single-Electron Transistors and Complementary Metal-Oxide-Semiconductor Field-Effect Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 1066
EP - 1070
AU - Ken UCHIDA
AU - Junji KOGA
AU - Ryuji OHBA
AU - Akira TORIUMI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.
ER -