The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 "저전력 직접 매핑 명령 캐시를 위한 새로운 아키텍처"를 제안합니다.기록 기반 태그 비교 (HBTC) 캐시. " 캐시는 불필요한 태그 검사를 피하기 위해 태그 비교 결과를 재사용하려고 시도합니다. 실행 공간은 확장된 BTB(Branch Target Buffer)에 기록됩니다. 평가에서 태그 비교에 필요한 에너지를 90 이상 줄일 수 있는 것으로 관찰되었습니다. 많은 응용 프로그램에서 %.
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Koji INOUE, Vasily G. MOSHNYAGA, Kazuaki MURAKAMI, "Omitting Cache Look-up for High-Performance, Low-Power Microprocessors" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 2, pp. 279-287, February 2002, doi: .
Abstract: In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache. " The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_279/_p
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@ARTICLE{e85-c_2_279,
author={Koji INOUE, Vasily G. MOSHNYAGA, Kazuaki MURAKAMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Omitting Cache Look-up for High-Performance, Low-Power Microprocessors},
year={2002},
volume={E85-C},
number={2},
pages={279-287},
abstract={In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache. " The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.},
keywords={},
doi={},
ISSN={},
month={February},}
부
TY - JOUR
TI - Omitting Cache Look-up for High-Performance, Low-Power Microprocessors
T2 - IEICE TRANSACTIONS on Electronics
SP - 279
EP - 287
AU - Koji INOUE
AU - Vasily G. MOSHNYAGA
AU - Kazuaki MURAKAMI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache. " The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.
ER -