The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
간단한 구조와 고속 동작회로, 큰 바이어스 마진을 갖춘 디멀티플렉서(DMUX)를 설계했습니다. 이진 트리 아키텍처와 클록 구동 회로를 사용하면 동일한 기본 회로, 즉 T-FF와 1-2 스위치로 구성된 1-2 DMUX에서 다중 채널 DMUX를 쉽게 구성할 수 있습니다. . 셀 레벨 최적화와 몬테카를로 시뮬레이션을 적용하여 회로의 바이어스 마진과 동작 주파수를 확대했습니다. 1-to-2 DMUX와 다중채널 DMUX, 즉 1-to-4 DMUX의 논리적 동작을 실험적으로 확인하였다. 마진도 큰 것으로 확인됐다.
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Futoshi FURUTA, Kazuo SAITOH, Kazumasa TAKAGI, "Design of Demultiplexer and Demonstration of the Operation up to 46 GHz" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 3, pp. 631-635, March 2002, doi: .
Abstract: We have designed a demultiplexer (DMUX) with a simple structure, high-speed operation circuits and large bias margins. By using a binary-tree architecture and clock-driven circuits, multi-channel DMUXs can be constructed easily from the same elemental circuits, i.e., 1-to-2 DMUX, consisting of a T-FF and a 1-to-2 switch. By applying cell-level optimization and Monte Carlo simulation, bias margins and operation frequency of the circuits were enlarged. Logical operations of the 1-to-2 DMUX and a multi-channel DMUX, e.g., a 1-to-4 DMUX were experimentally confirmed. It was also confirmed that the large margins,
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_3_631/_p
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@ARTICLE{e85-c_3_631,
author={Futoshi FURUTA, Kazuo SAITOH, Kazumasa TAKAGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of Demultiplexer and Demonstration of the Operation up to 46 GHz},
year={2002},
volume={E85-C},
number={3},
pages={631-635},
abstract={We have designed a demultiplexer (DMUX) with a simple structure, high-speed operation circuits and large bias margins. By using a binary-tree architecture and clock-driven circuits, multi-channel DMUXs can be constructed easily from the same elemental circuits, i.e., 1-to-2 DMUX, consisting of a T-FF and a 1-to-2 switch. By applying cell-level optimization and Monte Carlo simulation, bias margins and operation frequency of the circuits were enlarged. Logical operations of the 1-to-2 DMUX and a multi-channel DMUX, e.g., a 1-to-4 DMUX were experimentally confirmed. It was also confirmed that the large margins,
keywords={},
doi={},
ISSN={},
month={March},}
부
TY - JOUR
TI - Design of Demultiplexer and Demonstration of the Operation up to 46 GHz
T2 - IEICE TRANSACTIONS on Electronics
SP - 631
EP - 635
AU - Futoshi FURUTA
AU - Kazuo SAITOH
AU - Kazumasa TAKAGI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2002
AB - We have designed a demultiplexer (DMUX) with a simple structure, high-speed operation circuits and large bias margins. By using a binary-tree architecture and clock-driven circuits, multi-channel DMUXs can be constructed easily from the same elemental circuits, i.e., 1-to-2 DMUX, consisting of a T-FF and a 1-to-2 switch. By applying cell-level optimization and Monte Carlo simulation, bias margins and operation frequency of the circuits were enlarged. Logical operations of the 1-to-2 DMUX and a multi-channel DMUX, e.g., a 1-to-4 DMUX were experimentally confirmed. It was also confirmed that the large margins,
ER -