The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 나노미터 규모의 CMOS 트랜지스터를 설계하고 제조하는 데 있어 근본적인 과제와 가능한 솔루션을 다룹니다. 고급 게이트 유전체, 매우 얕은 접합, 채널 도펀트 프로파일 엔지니어링 및 살리사이드와 같은 필수 기술 구성 요소에 대해 논의합니다. 물리적 게이트 길이가 15nm에 불과한 초대형 트랜지스터는 기존 평면 CMOS 기술을 물리적 한계까지 밀어붙이려는 지속적인 노력의 일환으로 입증되었습니다.
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부
Bin YU, "CMOS Transistor in Nanoscale Era" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 5, pp. 1052-1056, May 2002, doi: .
Abstract: This paper addresses the fundamental challenges and possible solutions in designing and fabricating nanometer-scale CMOS transistor. Essential technology components such as advanced gate dielectrics, ultra-shallow junction, channel dopant profile engineering, and salicide are discussed. Ultra-scaled transistor with physical gate length down to 15 nm is demonstrated as a continued effort to push the traditional planar CMOS technology towards its physical limit.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1052/_p
부
@ARTICLE{e85-c_5_1052,
author={Bin YU, },
journal={IEICE TRANSACTIONS on Electronics},
title={CMOS Transistor in Nanoscale Era},
year={2002},
volume={E85-C},
number={5},
pages={1052-1056},
abstract={This paper addresses the fundamental challenges and possible solutions in designing and fabricating nanometer-scale CMOS transistor. Essential technology components such as advanced gate dielectrics, ultra-shallow junction, channel dopant profile engineering, and salicide are discussed. Ultra-scaled transistor with physical gate length down to 15 nm is demonstrated as a continued effort to push the traditional planar CMOS technology towards its physical limit.},
keywords={},
doi={},
ISSN={},
month={May},}
부
TY - JOUR
TI - CMOS Transistor in Nanoscale Era
T2 - IEICE TRANSACTIONS on Electronics
SP - 1052
EP - 1056
AU - Bin YU
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - This paper addresses the fundamental challenges and possible solutions in designing and fabricating nanometer-scale CMOS transistor. Essential technology components such as advanced gate dielectrics, ultra-shallow junction, channel dopant profile engineering, and salicide are discussed. Ultra-scaled transistor with physical gate length down to 15 nm is demonstrated as a continued effort to push the traditional planar CMOS technology towards its physical limit.
ER -