The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
0.1μm 미만 CMOS 장치의 문제를 극복하기 위해 소스-드레인과 게이트 영역이 겹치지 않는 MOSFET 구조가 제안되었습니다. 광범위한 시뮬레이션 연구를 통해 주요 장치 특성을 조사했습니다. 유전체 스페이서를 통한 프린징 게이트 전계는 비중첩 영역의 반전층을 유도하여 확장된 S/D 영역으로 작용합니다. 전자는 스페이서 아래에서 합리적으로 유도되었습니다. 내부 물리학과 속도 특성은 비중첩 거리를 통해 연구되었습니다. 제안된 구조는 중첩된 구조에 비해 문턱하부기울기와 DIBL 특성이 우수하였다.
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부
Hyunjin LEE, Sung-il CHANG, Jongho LEE, Hyungcheol SHIN, "Characteristics of MOSFET with Non-overlapped Source-Drain to Gate" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 5, pp. 1079-1085, May 2002, doi: .
Abstract: A MOSFET structure with non-overlapped source-drain to gate region is proposed to overcome the challenges in sub-0.1 µm CMOS device. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. Electrons were induced reasonably under the spacer. Internal physics and speed characteristics were studied with the non-overlap distance. The proposed structure had good subthreshold slope and DIBL characteristics compared to those of overlapped structure.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1079/_p
부
@ARTICLE{e85-c_5_1079,
author={Hyunjin LEE, Sung-il CHANG, Jongho LEE, Hyungcheol SHIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Characteristics of MOSFET with Non-overlapped Source-Drain to Gate},
year={2002},
volume={E85-C},
number={5},
pages={1079-1085},
abstract={A MOSFET structure with non-overlapped source-drain to gate region is proposed to overcome the challenges in sub-0.1 µm CMOS device. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. Electrons were induced reasonably under the spacer. Internal physics and speed characteristics were studied with the non-overlap distance. The proposed structure had good subthreshold slope and DIBL characteristics compared to those of overlapped structure.},
keywords={},
doi={},
ISSN={},
month={May},}
부
TY - JOUR
TI - Characteristics of MOSFET with Non-overlapped Source-Drain to Gate
T2 - IEICE TRANSACTIONS on Electronics
SP - 1079
EP - 1085
AU - Hyunjin LEE
AU - Sung-il CHANG
AU - Jongho LEE
AU - Hyungcheol SHIN
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - A MOSFET structure with non-overlapped source-drain to gate region is proposed to overcome the challenges in sub-0.1 µm CMOS device. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. Electrons were induced reasonably under the spacer. Internal physics and speed characteristics were studied with the non-overlap distance. The proposed structure had good subthreshold slope and DIBL characteristics compared to those of overlapped structure.
ER -