The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
새로운 경합없는 Domino 로직(CF-도미노) 이는 낮은 임계 전압에 특히 적합합니다(LVT)이 보고된다. LVT용 기존 Domino 회로에 비해 뛰어난 잡음 마진과 속도는 다음을 통해 입증됩니다. HSPICE(R) 시뮬레이션과 0.25V의 공급 전압을 갖춘 2.5μm CMOS 기술을 사용했습니다. 동적 및 누설 전력과 면적에 대한 새로운 기술의 영향을 평가했습니다. 면적을 3% 늘리고 노이즈 마진을 일정하게 유지한 새로운 CF-도미노 임계 전압이 20mV에서 450mV까지 확장되므로 기존 DOMINO보다 200% 더 적은 지연을 달성합니다. 또한 해당 임계값 전압에서 동적 전력은 13% 감소하고 누출은 5% 감소했습니다.
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부
Muhammad E.S. ELRABAA, Mohab H. ANIS, Mohamed I. ELMASRY, "A Contention-Free DOMINO Logic for Scaled-Down CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 5, pp. 1177-1181, May 2002, doi: .
Abstract: A new contention-free Domino logic (CF-Domino) that is especially suited for low threshold voltage (LVT) is reported. Its superior noise margin and speed over conventional Domino circuits for LVTs are demonstrated using HSPICE(R) simulations and a 0.25 µm CMOS technology with a supply voltage of 2.5 V. The impacts of the new technique on dynamic and leakage powers and area were evaluated. At a 3% area increase, and keeping the noise margins constant, the new CF-DOMINO achieves 20% less delay than conventional DOMINO as the threshold voltage scales from 450 mV down to 200 mV. It also achieved 13% less dynamic power and 5% less leakage at that threshold voltage.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1177/_p
부
@ARTICLE{e85-c_5_1177,
author={Muhammad E.S. ELRABAA, Mohab H. ANIS, Mohamed I. ELMASRY, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Contention-Free DOMINO Logic for Scaled-Down CMOS},
year={2002},
volume={E85-C},
number={5},
pages={1177-1181},
abstract={A new contention-free Domino logic (CF-Domino) that is especially suited for low threshold voltage (LVT) is reported. Its superior noise margin and speed over conventional Domino circuits for LVTs are demonstrated using HSPICE(R) simulations and a 0.25 µm CMOS technology with a supply voltage of 2.5 V. The impacts of the new technique on dynamic and leakage powers and area were evaluated. At a 3% area increase, and keeping the noise margins constant, the new CF-DOMINO achieves 20% less delay than conventional DOMINO as the threshold voltage scales from 450 mV down to 200 mV. It also achieved 13% less dynamic power and 5% less leakage at that threshold voltage.},
keywords={},
doi={},
ISSN={},
month={May},}
부
TY - JOUR
TI - A Contention-Free DOMINO Logic for Scaled-Down CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 1177
EP - 1181
AU - Muhammad E.S. ELRABAA
AU - Mohab H. ANIS
AU - Mohamed I. ELMASRY
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - A new contention-free Domino logic (CF-Domino) that is especially suited for low threshold voltage (LVT) is reported. Its superior noise margin and speed over conventional Domino circuits for LVTs are demonstrated using HSPICE(R) simulations and a 0.25 µm CMOS technology with a supply voltage of 2.5 V. The impacts of the new technique on dynamic and leakage powers and area were evaluated. At a 3% area increase, and keeping the noise margins constant, the new CF-DOMINO achieves 20% less delay than conventional DOMINO as the threshold voltage scales from 450 mV down to 200 mV. It also achieved 13% less dynamic power and 5% less leakage at that threshold voltage.
ER -