The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 3V 8비트 200MSPS CMOS 폴딩/보간 아날로그-디지털 변환기를 제안한다. FR(Folding Rate)이 8, NFB(Number of Folding Block)가 4, IR(Interpolating Rate)이 8인 효율적인 아키텍처를 사용합니다. SNR 향상을 위해 분산형 트랙 앤 홀드 회로가 전면에 포함되어 있습니다. 입력 단계 끝. 고속 및 저전력 동작을 달성하기 위해 개선된 동적 아날로그 래치가 제안되었다. 또한, 새로운 온도계 알고리즘과 지연 오류 보정 알고리즘을 기반으로 한 디지털 인코더를 제안한다. 이 칩은 0.35μm 2-폴리 3-금속 n웰 CMOS 기술로 제작되었습니다. 유효 칩 면적은 1200μm입니다.
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부
Sanghoon JOO, Minkyu SONG, "A 3V 8-Bit 200MSPS CMOS ADC with an Improved Analog Latch and a Novel Digital Encoder" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 8, pp. 1554-1561, August 2002, doi: .
Abstract: In this paper, a 3 V 8-bit 200MSPS CMOS folding/interpolation Analog-to-Digital Converter is proposed. It employs an efficient architecture whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improving SNR, distributed track and hold circuits are included at the front end of input stage. In order to obtain a high speed and low power operation, an improved dynamic analog latch is proposed. Further, a digital encoder based on a novel thermometer algorithm and a delay error correction algorithm is proposed. The chip has been fabricated with a 0.35 µm 2-poly 3-metal n-well CMOS technology. The effective chip area is 1200 µm
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_8_1554/_p
부
@ARTICLE{e85-c_8_1554,
author={Sanghoon JOO, Minkyu SONG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 3V 8-Bit 200MSPS CMOS ADC with an Improved Analog Latch and a Novel Digital Encoder},
year={2002},
volume={E85-C},
number={8},
pages={1554-1561},
abstract={In this paper, a 3 V 8-bit 200MSPS CMOS folding/interpolation Analog-to-Digital Converter is proposed. It employs an efficient architecture whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improving SNR, distributed track and hold circuits are included at the front end of input stage. In order to obtain a high speed and low power operation, an improved dynamic analog latch is proposed. Further, a digital encoder based on a novel thermometer algorithm and a delay error correction algorithm is proposed. The chip has been fabricated with a 0.35 µm 2-poly 3-metal n-well CMOS technology. The effective chip area is 1200 µm
keywords={},
doi={},
ISSN={},
month={August},}
부
TY - JOUR
TI - A 3V 8-Bit 200MSPS CMOS ADC with an Improved Analog Latch and a Novel Digital Encoder
T2 - IEICE TRANSACTIONS on Electronics
SP - 1554
EP - 1561
AU - Sanghoon JOO
AU - Minkyu SONG
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2002
AB - In this paper, a 3 V 8-bit 200MSPS CMOS folding/interpolation Analog-to-Digital Converter is proposed. It employs an efficient architecture whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improving SNR, distributed track and hold circuits are included at the front end of input stage. In order to obtain a high speed and low power operation, an improved dynamic analog latch is proposed. Further, a digital encoder based on a novel thermometer algorithm and a delay error correction algorithm is proposed. The chip has been fabricated with a 0.35 µm 2-poly 3-metal n-well CMOS technology. The effective chip area is 1200 µm
ER -