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Minkyu SONG, Kunihiro ASADA, "Design of a Conditional Sign Decision Booth Encoder for a High Performance 3232-Bit Digital Multiplier" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 9, pp. 1709-1717, September 2002, doi: .
Abstract: In this paper, a high performance 3232-bit multiplier for a DSP core is proposed. The multiplier is composed of a block of Booth Encoder, a block of data compression, and a block of a 64-bit adder. In the block of Booth encoder, a conditional sign decision Booth encoder that reduces the gate delay and power consumption is proposed. In the block of data compression, 4-2 and 9-2 data compressors based on a novel compound logic are used for the efficient compressing of extra sign bit. In the block of 64-bit adder, an adaptive MUX-based conditional select adder with a separated carry generation block is proposed. The proposed 3232-bit multiplier is designed by a full-custom method and there are about 28,000 transistors in an active area of 900 µm 500 µm with 0.25 µm CMOS technology. From the experimental results, the multiplication time of the multiplier is about 3.2 ns at 2.5 V power supply, and it consumes about 50 mW at 100 MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_9_1709/_p
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@ARTICLE{e85-c_9_1709,
author={Minkyu SONG, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a Conditional Sign Decision Booth Encoder for a High Performance 3232-Bit Digital Multiplier},
year={2002},
volume={E85-C},
number={9},
pages={1709-1717},
abstract={In this paper, a high performance 3232-bit multiplier for a DSP core is proposed. The multiplier is composed of a block of Booth Encoder, a block of data compression, and a block of a 64-bit adder. In the block of Booth encoder, a conditional sign decision Booth encoder that reduces the gate delay and power consumption is proposed. In the block of data compression, 4-2 and 9-2 data compressors based on a novel compound logic are used for the efficient compressing of extra sign bit. In the block of 64-bit adder, an adaptive MUX-based conditional select adder with a separated carry generation block is proposed. The proposed 3232-bit multiplier is designed by a full-custom method and there are about 28,000 transistors in an active area of 900 µm 500 µm with 0.25 µm CMOS technology. From the experimental results, the multiplication time of the multiplier is about 3.2 ns at 2.5 V power supply, and it consumes about 50 mW at 100 MHz.},
keywords={},
doi={},
ISSN={},
month={September},}
부
TY - JOUR
TI - Design of a Conditional Sign Decision Booth Encoder for a High Performance 3232-Bit Digital Multiplier
T2 - IEICE TRANSACTIONS on Electronics
SP - 1709
EP - 1717
AU - Minkyu SONG
AU - Kunihiro ASADA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2002
AB - In this paper, a high performance 3232-bit multiplier for a DSP core is proposed. The multiplier is composed of a block of Booth Encoder, a block of data compression, and a block of a 64-bit adder. In the block of Booth encoder, a conditional sign decision Booth encoder that reduces the gate delay and power consumption is proposed. In the block of data compression, 4-2 and 9-2 data compressors based on a novel compound logic are used for the efficient compressing of extra sign bit. In the block of 64-bit adder, an adaptive MUX-based conditional select adder with a separated carry generation block is proposed. The proposed 3232-bit multiplier is designed by a full-custom method and there are about 28,000 transistors in an active area of 900 µm 500 µm with 0.25 µm CMOS technology. From the experimental results, the multiplication time of the multiplier is about 3.2 ns at 2.5 V power supply, and it consumes about 50 mW at 100 MHz.
ER -